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Seth1er
Associate III
May 22, 2023
Question

Clock precision on a STM32L476

  • May 22, 2023
  • 5 replies
  • 1662 views

Hi all,

I need to drive the ADC with TIM1 at 4MHz, drive by an external event.

I want to know the clock precision on this timer.

For the moment I use HSI16 and the PLL to have 80MHz on APB.

I also have a LSE for the RTC.

but what is the precision. I need less than 1KHz on the 4MHz

can you help me to found this?

This topic has been closed for replies.

5 replies

waclawek.jan
Super User
May 22, 2023


_legacyfs_online_stmicro_images_0693W00000bkZFBQA2.pngJW

Seth1er
Seth1erAuthor
Associate III
May 22, 2023

Thank you, but for me, this is about HSI only.

what about the PLL? In my understand, a PLL can modify the accurate no?

and the Timer to .?

waclawek.jan
Super User
May 22, 2023

> PLL can modify the accurate no?

No. PLL can add jitter, but the long-term relative accuracy (i.e. how many % is it different from the required frequency) is the same as of the primary clock source (i.e. here HSI16). Same for timer, which is derived from PLL.

By multiplying (as in PLL) or dividing (as in prescalers and dividers) you can't change relative precision of frequency. You can increase precision by introducing some external, more precise source - either by calibration of the HSI (but don't hold your breath, it won't be too precise even after calibration, see trimming step in the above screenshot) or simply by deriving the frequency from a more precise source, i.e. crystal or crystal oscillator.

JW

Seth1er
Seth1erAuthor
Associate III
May 22, 2023

ok, if I understand, if the HSI have 100KHz drift (16.1MHz for example),

then with pll x20 / 4 to have 80MHz, I will have 500KHz drift, and finally, with a timer at 4MHz, I will have 25KHz drift, of course it's an exemple without temperature and voltage etc. It look huge for me, around 6% drift for an oscillator, where we generally have some ppm.

raptorhal2
Lead
May 22, 2023

I also have a LSE for the RTC.

Then use it. The MSI feeding the PLL is specifed to be better than 0.25% if autocorrected by the LSE.

Set the RCC->CR MSIPLLMode bit to one using:

HAL_RCCEx_EnableMSIPLLEN();

Without an HSE, that is probably the best you will get.