Clarification about internal tamper signals and interconnections

[JohnFrancis]

Section 36.6.1, Bit 18 (ITAMP3E) indicates that LSE frequency monitoring can be enabled. It appears that the hardware automatically detects when the LSE frequency goes above or below the defined thresholds and sets the ITAMP3F flag in the TAMP_SR register when an LSE failure occurs. When the LSE fails, ITAMP3 is triggered, which asserts the tamp_erase signal, and the backup registers are then automatically erased?

 

 

 

Edit: This discussion is related to Can backup registers persist when VBAT drops enoug... - STMicroelectronics Community 

[waclawek.jan]

Nice catch.

However, even if it is not properly documented, I suspect this is output from the LSECSS module. This to run, LSI has to be enabled, too (with implications on consumption), and it does not work in VBAT mode. See Clock security system on LSE subchapter of RCC chapter.

JW

[JohnFrancis]

Thanks for your response.

doubt regarding LSECSS and Internal Tamper 3 (ITAMP3):

For LSECSS:

• Chapter 7: Reset and Clock Control (RCC)

• Section 7.2.10: Clock security system on LSE

• Register: RCC_BDCR

RCC->BDCR |= RCC_BDCR_LSECSSON; // Enable LSECSS in RCC module

For Internal Tamper 3 (ITAMP3):

• Chapter 36: Tamper and Backup Registers (TAMP)

• Section 36.3.2: TAMP pins and internal signals

• Register: TAMP_CR1

 

TAMP->CR1 |= TAMP_CR1_ITAMP3E; // Enable ITAMP3 in TAMP module

Since these are different registers in different hardware blocks, it seems they operate independently. My understanding is:

• LSE fails → ITAMP3 detects the failure directly (inside the TAMP module, using the LSE clock) → triggers tamp_erase.

I cannot find any documented connection between ITAMP3 and LSECSS, so it appears they are independent? If that is the case, ITAMP3 might still work in VBAT mode, while LSECSS does not?

The reference manual provides very limited information about Internal Tamper 3, and there is no documentation explaining how ITAMP3 detects an LSE failure.

Please let me know the relationship (if any) between LSECSS and ITAMP3, and confirm whether ITAMP3 operates in VBAT mode. Thank you!

[JohnFrancis]

You are right, I think the internal tamper system does not work in VBAT mode.

I have tested the following:

• Connected VBAT through the RPS with the super‑capacitor isolated.

• The RTC stops operating at around 1.6 V, while the backup registers continue to work down to about 0.4 V.

• The internal tamper system did not detect the crystal failure (ITAMP3) on the LSE.

I think I may need to add external hardware for VBAT drops below 1.7V, trigger external tamper pin, but I don’t understand why ST hasn’t addressed such a basic requirement. With VBAT, they could at least provide a mechanism to detect when the RTC stops counting as the VBAT voltage drops below a threshold.

I’ve attached the VBAT vs RTC vs backup‑register results, hopefully others can make use of this in the future.