Change IWDG reload and prescaler live

[justin239955_st]

Posted on June 07, 2013 at 17:32

Following my last post on the subject of flash memory erase vs watchdog I have another concern.

Reading the spec I believe that I may be able to change the prescaler+reload of my watchdog just for the time that the flash perform it's erase operation. When i try to do that it does not seem to work even though the spec seems to says so. Here's the code:

I have this method to init the wd:

void EnableWatchdog(uint16_t watchTimeMs) {

&sharpifdef ENABLE_WATCHDOG // See app.h

IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable);

IWDG_SetPrescaler(IWDG_Prescaler_4); // RTC clock = LSI (40kHz) / 4 = 10kHz

IWDG_SetReload(10 * watchTimeMs); // 10 * X / 10kHz = Xms timeout

IWDG_WriteAccessCmd(IWDG_WriteAccess_Disable);

IWDG_Enable();

&sharpendif

}

During init I call EnableWatchdog(3);

Later i will call this:

if(IWDG->SR == 0) {

SetTP(TP1, Bit_SET);

EnableWatchdog(10);

timeRti = PCtrl;

while((PCtrl - timeRti) < m_msf2rti(5)) { } // Test watchdog

SetTP(TP1, Bit_RESET);

}

The deal with timeRti is only to block the mcu during a specific time to see if watchdog works.

So This will block the mcu 5ms and if the watchdog is still 3ms (from init) the mcu will reset non-stop. If the the EnableWatchdog(10); works it will not reset and i will se my tp1 toggle accordingly. I watch IWDG->SR because the spec says i should not update the prescaler or reload if any of the status bits are still set.

The mcu resets non-stop. Any thoughts?

#stm32-iwdg-watchdog

[mmensch]

Posted on August 21, 2013 at 15:56

Hi,

I came across a similar problem.

Because reference manual says:

Configuring the IWDG when the window option is disabled

When the window option it is not used, the IWDG can be configured as follows:

1. Enable register access by writing 0x0000 5555 in the IWDG_KR register.

2.  Write the IWDG prescaler by programming IWDG_PR from 0 to 7.

3.  Write the reload register (IWDG_RLR).

4.  Wait for the registers to be updated (IWDG_SR = 0x0000 0000).

5.  Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA).

6.  Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR.

I added this line in my IWDG initalization:

while ((IWDG->SR & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0) {}

But it never comes past this line.

And IWDG also works without it (or seems to )

STM32F051 Errata sheet says nothing about it. Any hints about the right way to configure IWDG are welcome.

Martin