Change DMA_CPARx and DMA_CMARx while DMA is enabled?

[Singh.Harjit]

Has anyone tried it and knows that it works/doesn't work?

I can guarantee that a DMA request will not occur during the update of these registers.

This would be on an STM32G474. I don't have my board as yet, so, can't try it.

[waclawek.jan]

I personally wouldn't even try to do this.

Why can't you stop and restart?

JW

[MasterT]

Read RM0440 DMA section. There is a note:

" Note: this register is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1)."

[Singh.Harjit]

@Community member​ The DMA control register is at a lower address than the address registers. So, I'd have to use two chained DMA channels to accomplish this. First DMA channel to update the address and the second to update the control register.

@MasterT​ Thank you - I've seen it and was wondering if anyone had tried it.

Please see more details in this thread: https://community.st.com/s/question/0D73W000001Hv9c/detail?s1oid=00Db0000000YtG6&s1nid=0DB0X000000DYbd&emkind=chatterCommentNotification&s1uid=0050X000007vmFR&emtm=1628687912532&fromEmail=1&s1ext=0

[MasterT]

Compare to RM0390:

Bits 31:0 PAR[31:0]: peripheral address

Base address of the peripheral data register from/to which the data is read/written.

These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR

register.

Making logical conclusion, I see an error (contradiction) in RM0440, should be :

" Note: this register is set and cleared by software.

It must not be written when the channel is enabled (EN = 1).

It is not read-only when the channel is enabled (EN = 1)."

Regarding another thread, you can "sync" OPA MUX using timer, same timer can also trigger ADC conversion, though data array would hold two inputs "interleaved".

Ones I did same trick with DAC's (non-bufferes fast 15 msps), I cascaded 2-dacs output to first MUX-OPA, than chain two OPA outputs to next stage MUX-OPA.

Doing so I increased sampling conversion by 4X, bringing to 60 msps. All machine was synchronized using 3 or 4 timers, DAC triggers, than 1-st MUX, than 2-nd MUX.

[Amel NASRI]

Hi @MasterT​ ,

I confirm this typo: "not" is inserted by error in some occurrences of the note while describing DMA registers bit-fields.

The action is taken to make required corrections. Thanks for bringing it to our attention.

-Amel

[Singh.Harjit]

@MasterT​ Thank you for the info.

@Imen GH​ @Igor Cesko​ Can you comment on @MasterT​ comment about the RM0390 VS RM0440, please about whether the DMA_CPARx, DMA_CMARx, DMA_CNDTx are write protected based on the enable bit state or not. Thank you.