CCM on STM32F405 and STM32F446

[frank23]

Posted on September 03, 2015 at 13:57

Hi, 

We are using STM32F303 in one of our project and find the CCM routine booster is of great help. Now, we are openning a new project using F4, but the CCM programming information is very limited on F4. My questions are:

1. F405 datasheet clearly said it has CCM, will the program running in CCM still 30% faster than program running in flash?

2. Where can I find the CCM programming guide for F4?

3. Do F446 also has CCM? The datasheet didn't mention this.

Thank you!

Frank 

#ccm #f405 #f446

[Tesla DeLorean]

Posted on September 03, 2015 at 15:06

The CCM on the F405 is connected to the Data side of the core, you can't run code from it.

The ART on the F4 is very effective at hiding the speed of the FLASH, and the prefetched path is faster than SRAM.

For the F446 you want to look at the

http://www.st.com/web/en/resource/technical/document/datasheet/DM00141306.pdf

, check the Multi-AHB Matrix. There is no CCM RAM connected to the core, there is 128K of SRAM[1/2] situated in two banks starting at 0x20000000

[frank23]

Posted on September 04, 2015 at 15:07

Hi, 

Thank you so much! So, F4's CCM function is totally different with F3, what is its purpose, can user put  a data array into it? 

How to use the CCM 

to boost specific critical routine

, is it user accessible or the CPU manage it automaticly like ''L1/L2'' cache?Anything need to be done in the compiler?

T

he F446 don't have CCM, will it be slower than F405? 

Frank

[Tesla DeLorean]

Posted on September 04, 2015 at 18:17

The M3/M4 do not architecturally support caching, the ART is a cache/prefetch engine on a wide FLASH data bus. In most circumstances it's going to run on the 405 as fast as SRAM.

The CCM RAM can be used for arrays and stacks, you cannot use DMA on it, and there is no contention on it from DMA activity that might be occurring on other SRAM banks. It's tightly coupled to the core.

It's mapped into regular memory space, it is accessed like any other. It has a clock enable, but as I recall that's enabled by default. It's 64KB but it's not contiguous with the other SRAM. You'd need to add and manage the region supplied to the linker (vs scripts or scatter files), and directives or pragmas on the compiler side.

The F446 and F405 will have similar performance numbers. If you're doing a lot of heavy DMA, you might want to watch SRAM banks you're using for that, and processing.