Cant use internal watchdog while using flash

[HZaib.1]

hi I am using stm32l496 and when I use flash the watchdog gives error for some reason. and if for some reason flash works the watchdog always fails.

Is there any solution anyone else has faced this issue ?

[Bob S]

"while using flash" ??? Do you mean code running from FLASH (I suspect not)? Or do you mean when you try erasing/programming flash from your code?

And by "internal watchdog" do you mean the "independent watchdog" (IWDG) or system window watchdog (WWDG)?

What error do you get? And showing some code might help.

What is the watchdog timeout period? And how long does it take to erase or program flash? I don't recall if the L496 has dual-bank flash. But if you attempt to execute code from the same flash bank that is being erased/programmed, the CPU will stall until the FLASH operation is complete. That means no watchdog servicing during FLASH operations. You may need to move critical code into RAM so that it can run while programming FLASH.

[HZaib.1]

hi thanks for your reply.

My system is running Freertos cmsis V2 version.

Let me start from the beginning. When I started building the whole system, Internal flash requirement was not given yet as we are already using external flash. But later in development, we kept internal flash as a fail safe measure. Now before implementing internal flash code IWDG was working as it suppose to. And when I implemented flash code, the flash code always use to give error while erasing the program and even while saving something to it. So I debugged that problem to be with IWDG. After disabling IWDG flash started working fine, but now IWDG always fails on startup like it does not even initiate the IWDG and fails.

Internal flash function is kept in critical section of the code and it only executes on some circumstances which are rare.

1)first piece of code is my flash function and how I am writing to it.

2)2nd piece of code is my watchdog function and where the error is occuring

//This is piece of code how I am writing to flash 
GLOBAL UBYTE fda_Write ()
{
	hw_IntSav();			// disable interrupts
 
 
	osKernelLock();
 
	save_parameter(); //function that writes to flash
 
	osKernelUnlock();
 
	hw_IntRes();			// renable interrupts
 
}
 
void save_parameter(void)
{
	//UBYTE *ipFlaPar;		// Zeiger auf Parametertabelle im Flash
	uint64_t QuellAdr = (uint64_t)&Par;
	//char *buf = "hello worlddddddd aaaaaaaaaaaa";
	//uint64_t QuellAdr = (uint64_t )&buf;
	uint32_t ZielAdr;
	uint32_t WrAdr;
	uint32_t PAGEError;
 
 
 
	static FLASH_EraseInitTypeDef EraseInitStruct;
 
	 HAL_FLASH_Unlock();
 
 
 
 
 
	 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPTVERR);
	 EraseInitStruct.TypeErase = FLASH_TYPEERASE_PAGES;
	 EraseInitStruct.Banks = GetBank(0x080df800);
	 EraseInitStruct.Page = GetPage(0x080df800);
	 EraseInitStruct.NbPages = 1 + (sizeof(struct ParStruct) / FLASH_PAGE_SIZE);
 
	 if (HAL_FLASHEx_Erase(&EraseInitStruct, &PAGEError) != HAL_OK)
	 {
	 HAL_FLASH_Lock();
	 return ;
	 }
 
 
	 // Par-Flash schreiben
 
	 ZielAdr =0x080df800 + sizeof(struct ParStruct); /* - FLASH_DOUBLE_SIZE))*/
	 WrAdr = 0x080df800; // Pointer on 1st entry
 
	 while (WrAdr < ZielAdr)
	 {
	 if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_DOUBLEWORD, WrAdr, *(uint64_t *)QuellAdr) == HAL_OK)
	 {
	 WrAdr += 8;
	 QuellAdr += 8;
	 }
	 else
	 {
 
	 HAL_FLASH_Lock();
	 return ;
 
	 }
	 }
	 HAL_FLASH_Lock();
 
 
}

static void MX_IWDG_Init(void)
{
 
 /* USER CODE BEGIN IWDG_Init 0 */
 
 /* USER CODE END IWDG_Init 0 */
 
 /* USER CODE BEGIN IWDG_Init 1 */
#ifdef IWDG_Code_Disable
 /* USER CODE END IWDG_Init 1 */
 hiwdg.Instance = IWDG;
 hiwdg.Init.Prescaler = IWDG_PRESCALER_4;
 hiwdg.Init.Window = 4095;
 hiwdg.Init.Reload = 4095;
 if (HAL_IWDG_Init(&hiwdg) != HAL_OK)
 {
 Error_Handler();
 }
 /* USER CODE BEGIN IWDG_Init 2 */
#endif
//This is my timing set here
 hiwdg.Instance = IWDG;
 hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
 hiwdg.Init.Window = IWDG_WINDOW_DISABLE;
 hiwdg.Init.Reload = 500;
 if (HAL_IWDG_Init(&hiwdg) != HAL_OK) //code always fail here 
 {
 Error_Handler();
 }
 /* USER CODE END IWDG_Init 2 */
 
}
 
 
//I debugged the issue and failure lies here 
 /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
 0x5555 in KR */
 IWDG_ENABLE_WRITE_ACCESS(hiwdg);
 
After executing this the system goes into error handler