Can STM32F7 SPI-slave handle 32-bit packets, without DMA, under all circumstances?

[arnold_w]

I am working with the STM32F7 microcontroller and I would like to be able to send/receive 32-bit packets across an SPI-slave that is not using DMA. Will this be possible even if I can't guarantee to fill/empty the SPIx->DR register within a certain amount of time? (There are control pins that prevent several 32-bit packets from being transmitted before the previous one has been handled.) I am hoping that I can prepare the packet to be sent by assigning data (upper and lower words of 32-bit packet, respectively) to SPIx->DR twice, the first assignment will result in the upper word being fed into the FIFO and the second assignment will store the lower word in the SPIx->DR-register. Likewise, to retrieve the received 32-bit packet I would read SPIx->DR twice and then assemble the two (upper and lower) 16-bits words into a 32-bit word. Is this doable or have I misunderstood how the internal of the SPI-module works?

[S.Ma]

Assuming your SPI 32 bit RX and TX FIFO are empty, then preload the TX FIFO with the 32 bit data to be sent, in theory and not looking beyond this 32 bit transfer, you should be fine.

[berendi]

Yes, it should work. The FIFO can hold 32 bits. I would do something like this on the slave side

• Write SPI->DR twice
• Toggle or pulse the slave ready control signal
• Wait for rising edge of NSS (polling the GPIO input or using EXTI interrupt)
• Read SPI->DR twice
• Repeat.

On the master side, just look for edges on the control line, using an EXTI or a timer input channel, polling a status bit or enabling the interrupt.

This way, there are no events that need immediate attention either from the master or from the slave.

[arnold_w]

Ok, this sounds good. Could I perhaps even make the packet size 6 bytes then?

[berendi]

More than 4 bytes would require DMA​ or a low latency interrupt handler. I don't think there is a way around that.

[S.Ma]

For a high bitrate SPI bus, DMA in cyclic mode with some little SW tricks gets an SPI Slave more efficient...

Otherwise, FIFO is 32 bit, you get interrupt once the first word is loaded to the DR, so if you can refill the DR before the FIFO gets empty by interrupt in worst case scenario, you will get the yes/no answer.