Can stalled IRQs be interrupted by IRQ in RAM?

[Jnevi.1]

Hi,

i'm dealing with the window watchdog.

as my program erases a sector in flash i created a watchdog irq handler in RAM which retriggers the watchdog wen the sector is erased.

my Watchdog irq has the highest priority. all other irqs have lower priority

NVIC_InitStructure.NVIC_IRQChannel=WWDG_IRQn;
 NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority=0x00;
 NVIC_InitStructure.NVIC_IRQChannelSubPriority=0x00;
 NVIC_InitStructure.NVIC_IRQChannelCmd=ENABLE;
 NVIC_Init(&NVIC_InitStructure);

As far as i can tell my watchdog irq runs completly from RAM.

I ran some tests (don't trigger the watchdog from my mainloop) and i jump into the irq handler and can extend my watchdog window. so i think in principal this code works and the movment to RAM was successful.

but as soon as i start to erase a sector the watchdog retriggering does not work and i run into the watchdog reset.

there can happen other irqs with lower priority whichshould be stalled as they are not run from RAM.

Should my watchdog RAM handler be able to interrupt these stalled IRQs(this was my expactation) or do i have to disable ALL other IRQs which do run from Flash as stalled IRQs are not interruptable?

Thanks for clarification

[Jnevi.1]

Oh, i use an stm32f407 and this is my scatter file which is more or less the Keil example

LR_IROM1 0x08010000 0x00070000 { ; load region size_region
 ER_IROM1 0x08010000 0x00070000 { ; load address = execution address
 *.o (RESET, +First)
 *(InRoot$$Sections)
 .ANY (+RO)
 }
 RW_IRAM1 0x20000300 0x0001FE00 { ; RW data
 .ANY (+RW +ZI)
 }
 
 RW_CODE 0x20000200 OVERLAY 0x00000080 { ; RW data
 *.o (RAMCODESECTION)
 }
 
 RW_TEMP 0x20000280 OVERLAY 0x00000010 { ; RW data
 *.o (TEMPDATASECTION)
 }
}

[Jnevi.1]

this is my interrupt vector table and as far as i can tell the wwdg handler points to a RAM location(the 0x20000201 address)

memcpy((void*)0x20000000,(void const*)(FLASH_BASE | VECT_TAB_OFFSET), 0x1FF); // Move Vector Table from FLASH to RAM
 SCB->VTOR = SRAM_BASE ; /* Vector Table Relocation in Internal SRAM */

[Jnevi.1]

ok, was my question to special or not good enough? ;)

[waclawek.jan]

Which STM32?

As soon as *any* code attempts to read from FLASH which is being currently erased, the processor will be stalled. It cannot resume from this stall by interrupt of any priority, the only way to resume is to wait until FLASH operation (erase) finishes.

So, the only way to avoid the watchdog reset is to

• run the code which executes the FLASH erase from RAM, and remain with "main" there until FLASH is erased
• have *all* active interrupts (plus the vector table) in RAM
• no part of the running code (i.e. not the "main" nor the interrupts) may read any data from FLASH

Some STM32s have dual-bank FLASH; there you may erase (or write to) one bank while running from the other.

JW

[Jnevi.1]

thanks for making this clear!!!

i have the stm32f407 with one flash bank.

but now i'm sure i have to put my flash code in RAM also. before this was unclear to me as i thought the EWI wwdg irq could still be served if it is in RAM even in stalled processor mode

[Tesla DeLorean]

The stall is achieved by stuffing wait states, it blocks the core at a very fundamental level such that the execution pipeline stops.​

[Oliver Sedlacek]

Remember the vector table also needs to be in RAM