Can someone explain the DMAMUX mapping on the STM32G431?

[BTrem.1]

I read the ref manual several times but it is still unclear to me. I have a problem with a DMA design that is transferring TIM8_CH1 and TIM8_CH3 to memory using DMA_Channel1 and DMA_Channel2. I am getting a transfer error so am looking at what could cause this.

The timer value is uint32_t and the buffers are both 4-byte aligned. Is this okay? (I think so)

I do not understand the DMAMUX explanation in the ref manual page RM0440, page 384 Table 80. I see TIM8_CH1 is on DMA input request #49 and TIM8_CH3 is on DMA input request #51. How do these map to DMA Channel # on DMA1 and DMA2?

Can TIM8_CH1 and TIM8_CH3 be used respectively on DMA1_Channel1 and DMA1_Channel2. I can't seem to answer this from the ref manual do to my lack of understanding the explanation. The tables for the F303x and L41x are much clearer.

My understanding is a transfer error is caused by a bus fault, such as an illegal address. My destination data buffers are at 0x2000000C and 0x20000034. Are these an issue?

Thanks for any clarification you can offer, much appreciated.

BT

[BTrem.1]

Okay, I reduced my code to a minimum that was only running the DMA as described above. With TIM8 running and using capture on CH1 and CH3 I was able to trigger DMA1_CH1 and DMA2_CH2. Incidentally, this is using an external trigger on CH1 and a software trigger on CH3.

Whatever problem I am having in my complete code is not a problem with this Timer/DMA configuration. It still stands the DMAMUX documentation on the STM32G431 really fails compared to other ST devices. With 2127 pages in the Ref Manual they failed to communicate.

[Amel NASRI]

Hi @BTrem.1​ ,

A complementary content to what is already provided in the reference manual regarding DMA request multiplexer is provided in AN5224 (STM32 DMAMUX: the DMA request router).

Depending on the product where this multiplexer is available, this application note explains its features. It explains as well how to properly configure it.

-Amel