Can I interface 10 SRAMs using FMC controller and external address decoder for generating chip select signals.

[Agour.1]

I need to interface 10 SRAMs (1024 x 16). With existing FMC controller I can interface only 4 so I am planning to use address line decoder for generating chip select signals. My main concern is whether I would need to use external buffers & transceivers for address & data bus for meeting this increased fan out requirement.