Can FMC of STM32H7 have dram and sram enabled at the same time

[Martin Meijerman]

Posted on July 11, 2018 at 08:38

Dear Community,

Reading the datasheet and reference manual of the STM32H7 I am left wondering whether if it is possible to have both the DRAM and NOR/SRAM controllers of the FMC controller active at the same time?

The manuals describe the separate controllers within the FMC as separate entities. I have not been able to find explicit confirmation (nor denial) of whether it is also allowed/possible to activate more than one controller.

If it is possible, how would access to the bus be controlled?

Has anybody done this or confirm that this could actually be done?

Thanks!

Martin

#stm32h7

[Martin Meijerman]

Posted on July 12, 2018 at 07:57

For anybody with the same question.

I got an answer from St support (took 3 weeks, that is why I asked the question here too):

It is indeed possible to use SRAM and SDRAM at the same time (while sharing some signals). The FMC is capable of switching between the two while reliably managing the SDRAM so data corruption wouldn't be risked because of prolonged refresh.

[Tesla DeLorean]

Posted on July 12, 2018 at 08:38

Wouldn't the STM32H743I-EVAL tend to demonstrate this?