Calculate the frequency of the QUADSPI.

[Saif]

I have developped a graphical demo with the STM32H735 discovery kit, and the minimum frequency of the OCTOSPI to have a clean display is 66 MHz (framebuffer = 480x272x32). 

Now I want to use in my application an External RAM with QUADSPI (framebuffer = 640x480x16) I want to know what is the minimum frequency of QUADSPI to have the same performance?

Best Regards,

Saif.

[Aime]

Hi @Saif​ ,

Thank you for sharing your request.

In fact the QUADSPI is an another way to configure your OCTOSPI peripheral.

So all the specifications applying to the OCTOSPI are true in case of QUADSPI configuration.

Please find in attached the datasheet and refer to the section 6.3.20 "Octo-SPI Interface characteristics" for more details.

Best Regards,

A.MVE

[Saif]

Hi @Aime​ 

Thanks for your reply.

I didn't properly explain what I was asking for. I put my question differently.

I am talking about the bandwidth of the external RAM.

How do I calculate the bandwidth of a QUADSPI external SDRAM?

Best Regards,

Saif.

[Tesla DeLorean]

It's apt to be bandwidth constrained, and has some overhead is switching between different memory streams. Efficiencies here are derived from long burst transactions to advancing memory locations.

Is there perhaps a DK/DISCO board where you can measure the throughput, and see if the LTDC vs MCU interactions with the memory conflict enough that the screen tears?

[Alex - APMemory]

Hi,

To support your frame buffering 640x480x16, you need at least 35MB/s effective BW. I'll suggest to run the QSPI RAM closed to full speed (72MB/s BW) so at 133MHz for 3V or 144MHz for 1.8V

Regarding density, you may be able to deal with 16Mb (APS1604M-SQR-SN) but 64Mb (APS6404L-SQR-SN) might more confortable.

Please note STM32H7xx has limitation to run QSPI SDR and doesn't support Memory mapped Write mode. There are no limitation with OPI (APS6408L-OBM-BA) or QSPI DDR (APS12804-SQRH-WA)

Alex

[Tesla DeLorean]

The H72x/H73x and H7Ax/H7Bx, are both significantly different, are OCTOSPI, and also different from the earlier/original H74x/75x

640x480 16bpp at 60Hz is upward of 37MBps just to paint the display. The burst rates are apt to be higher as this doesn't account for the sync/porch timings.

Its the ability to read/write into the memory and interleave those operations is of primary concern, and then the ability to perform updates within much shorter windows with the horizontal refresh.

TBH most of the STM32 architecture assumes the performance of internal memories, or wide lane SDRAM. There not a lot of caching or use of more exotic stream/thread management with the memories.

[Alex - APMemory]

From our point of experience and customer use case, supporting frame buffering with QSPI SDR, QSPI DDR or OPI is most optimized solution, specifically taking into account pin count saving, and Power when needed. QSPI SDR might fit this case in general, but with H7 QSPI DDR or OPI would be needed

Alex