Bytewide DMA to a port: RAM to PD8-PD15, with a timer PWM used to generate /WR signal
Bytewide DMA to a port: RAM to PD8-PD15, with a timer PWM used to generate /WR signal.
I wonder if this will work. Some of it is a grey area. This is for loading a buffer into a ST7789 LCD controller, 66ns shortest cycle time.
TIM1 and DMA1 are already used in my project.
Digging around, it looks like TIM8 -> DMA2 should work, and a byte write to ODR+1 should land in ODR[15:8] and drive PD8-PD15.
It also looks like PC6-8 can be used for the PWM output to produce the /WR. The timer overflow loads the next byte, so you have to load the 1st byte manually.
There are some gotchas with spurious TIM behaviour. People found that with TIM8_UP, when you enable the timer, if the UGEN (update generation) bit or the initial configuration causes an immediate update event, you can get a spurious first trigger. You may have to set the UDIS bit or clear the update flag carefully, or use the ARPE/preload setup so the first genuine overflow is the first DMA trigger. One methid is after configuring TIM8 but before enabling the DMA request, set the UG bit (EGR.UG) to force a known update that loads the preload registers, then clear the update flag (SR.UIF), then enable the DMA request (DIER.UDE), then enable the counter.
The biggest question mark is the ODR+1 and byte write aspect. I also don't want to write stuff to PD0-PD7 since some of those are outputs.
DMA to BSRR would need a specially loaded source buffer, not just the data bytes.
Is the above feasible?
