BUG with STM32H723ZGT6 in SPI1 SCLK on PG11 pin (missing)

[Linas L]

Hello,

I am making SPI DAC update function, and I could not get PG11 to output SPI1 clock.

While if I switch to PB3 pin, all is perfect. (this is alternate pin for SPI1)

If I toggle PG11 as GPIO, I get waveform so where is no short or something similar. Errata is also mute about this....

LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG);
 
LL_GPIO_SetPinMode(GPIOG, LL_GPIO_PIN_11, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetAFPin_0_7(GPIOG, LL_GPIO_PIN_11, LL_GPIO_AF_5);
LL_GPIO_SetPinSpeed(GPIOG, LL_GPIO_PIN_11, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinPull(GPIOG, LL_GPIO_PIN_11, LL_GPIO_PULL_DOWN);
LL_GPIO_SetPinOutputType(GPIOG,LL_GPIO_PIN_11,LL_GPIO_OUTPUT_PUSHPULL);

This is don't work. I get low level all the time... But if I switch to PB3, all is great:

LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB);
 
LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_3, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetAFPin_0_7(GPIOB, LL_GPIO_PIN_3, LL_GPIO_AF_5);
LL_GPIO_SetPinSpeed(GPIOB, LL_GPIO_PIN_3, LL_GPIO_SPEED_FREQ_HIGH);
LL_GPIO_SetPinPull(GPIOB, LL_GPIO_PIN_3, LL_GPIO_PULL_DOWN);
LL_GPIO_SetPinOutputType(GPIOB,LL_GPIO_PIN_3,LL_GPIO_OUTPUT_PUSHPULL);

So, what I am doing wrong ? I can't find it 

Bonus question. I am running DMA, and i was hoping that TC will be after all data has been tranmited. Well, I get TC after 200ns, while it takes 100us to send data....

Any idea how to solve this?

I don't understand why ST can't include NSS hardware that would be handled with DMA transfers, it is just a few more triggers inside silicon to produce... NSS handling is just a mess.

[TDK]

> LL_GPIO_SetAFPin_0_7(GPIOG, LL_GPIO_PIN_11, LL_GPIO_AF_5);

For pin 11, you want LL_GPIO_SetAFPin_8_15.

LL_GPIO_SetAFPin_8_15(GPIOG, LL_GPIO_PIN_11, LL_GPIO_AF_5);

[Linas L]

Ahhh, as always, it's so obvious now..... It works,

Thank you for saving me a lot of time :smiling_face_with_smiling_eyes:

For every one else trying SPI code, here it is:

 LL_SPI_InitTypeDef spi_initstruct = {0};
 LL_GPIO_InitTypeDef GPIO_InitStruct = {0};
 LL_RCC_SetSPIClockSource(LL_RCC_SPI123_CLKSOURCE_CLKP);
 
 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SPI1);
 
 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOA);
 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOG);
 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOC);
 //LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_GPIOB);
 /**SPI1 GPIO Configuration
 PA7 ------> SPI1_MOSI
 PG10 ------> SPI1_NSS
 PG11 ------> SPI1_SCK
 PA6 ------> ISO_IN1
 PC4 ------> ISO_IN2
 */
 GPIO_InitStruct.Pin = LL_GPIO_PIN_10|LL_GPIO_PIN_15;
 GPIO_InitStruct.Mode = LL_GPIO_MODE_OUTPUT;
 GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_MEDIUM;
 GPIO_InitStruct.OutputType = LL_GPIO_OUTPUT_PUSHPULL;
 GPIO_InitStruct.Pull = LL_GPIO_PULL_NO;
 LL_GPIO_Init(GPIOG, &GPIO_InitStruct);
 
 LL_GPIO_SetOutputPin(GPIOG,LL_GPIO_PIN_10);
 
 GPIO_InitStruct.Pin = LL_GPIO_PIN_6;
 GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT;
 GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
 GPIO_InitStruct.Pull = LL_GPIO_PULL_DOWN;
 LL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 
 GPIO_InitStruct.Pin = LL_GPIO_PIN_4;
 GPIO_InitStruct.Mode = LL_GPIO_MODE_INPUT;
 GPIO_InitStruct.Speed = LL_GPIO_SPEED_FREQ_LOW;
 GPIO_InitStruct.Pull = LL_GPIO_PULL_DOWN;
 LL_GPIO_Init(GPIOC, &GPIO_InitStruct);
 
 
 LL_GPIO_SetPinMode(GPIOG, LL_GPIO_PIN_11, LL_GPIO_MODE_ALTERNATE);
 LL_GPIO_SetAFPin_8_15(GPIOG, LL_GPIO_PIN_11, LL_GPIO_AF_5);
 LL_GPIO_SetPinSpeed(GPIOG, LL_GPIO_PIN_11, LL_GPIO_SPEED_FREQ_HIGH);
 LL_GPIO_SetPinPull(GPIOG, LL_GPIO_PIN_11, LL_GPIO_PULL_DOWN);
 LL_GPIO_SetPinOutputType(GPIOG,LL_GPIO_PIN_11,LL_GPIO_OUTPUT_PUSHPULL);
 
 LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_7, LL_GPIO_MODE_ALTERNATE);
 LL_GPIO_SetAFPin_0_7(GPIOA, LL_GPIO_PIN_7, LL_GPIO_AF_5);
 LL_GPIO_SetPinSpeed(GPIOA, LL_GPIO_PIN_7, LL_GPIO_SPEED_FREQ_HIGH);
 LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_7, LL_GPIO_PULL_DOWN);
 
 spi_initstruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV128;
 spi_initstruct.TransferDirection = LL_SPI_SIMPLEX_TX;
 spi_initstruct.ClockPhase = LL_SPI_PHASE_1EDGE;
 spi_initstruct.ClockPolarity = LL_SPI_POLARITY_LOW;
 spi_initstruct.BitOrder = LL_SPI_MSB_FIRST;
 spi_initstruct.DataWidth = LL_SPI_DATAWIDTH_8BIT;
 spi_initstruct.NSS = LL_SPI_NSS_SOFT;
 spi_initstruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
 spi_initstruct.Mode = LL_SPI_MODE_MASTER;
 
 LL_SPI_Init(SPI1, &spi_initstruct);
 
 ISO_DAC_OFFSET = 0xAABB;
 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
 
 
 NVIC_SetPriority(DMA1_Stream7_IRQn, 0);
 NVIC_EnableIRQ(DMA1_Stream7_IRQn);
 
 LL_DMA_ConfigTransfer(DMA1,
 LL_DMA_STREAM_7,
 LL_DMA_DIRECTION_MEMORY_TO_PERIPH | LL_DMA_PRIORITY_HIGH | LL_DMA_MODE_NORMAL |
 LL_DMA_PERIPH_NOINCREMENT | LL_DMA_MEMORY_INCREMENT |
 LL_DMA_PDATAALIGN_BYTE | LL_DMA_MDATAALIGN_BYTE);
 
 LL_DMA_ConfigAddresses(DMA1,
 LL_DMA_STREAM_7,
 0x24000000, (uint32_t) &(SPI1->TXDR),
 LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_STREAM_7));
 
 LL_DMA_SetDataLength(DMA1, LL_DMA_STREAM_7, 2);
 LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_7, LL_DMAMUX1_REQ_SPI1_TX);
 LL_DMA_EnableIT_TC(DMA1, LL_DMA_STREAM_7);
 
 LL_DMA_EnableIT_TE(DMA1, LL_DMA_STREAM_7);
 
 LL_SPI_Enable(SPI1);
 /* Enable DMA Stream Tx */
 LL_DMA_EnableStream(DMA1, LL_DMA_STREAM_7);
 /* Master transfer start */
 LL_SPI_StartMasterTransfer(SPI1);
 

[TDK]

> I don't understand why ST can't include NSS hardware that would be handled with DMA transfers, it is just a few more triggers inside silicon to produce... NSS handling is just a mess.

The STM32H7 series has newer SPI peripheral where the SS pin can probably act as you want. Have you tried it?

[Linas L]

I would love to ,

So changed:

spi_initstruct.NSS = LL_SPI_NSS_HARD_OUTPUT;
LL_SPI_SetNSSPolarity(SPI1,LL_SPI_NSS_POLARITY_HIGH); //Or low...
LL_SPI_SetTransferSize(SPI1,1);
LL_SPI_SetMasterSSIdleness(SPI1,2);
 
LL_SPI_Enable(SPI1);
LL_DMA_EnableStream(DMA1, LL_DMA_STREAM_7);
LL_SPI_StartMasterTransfer(SPI1);

And lets not forget PIN init:

 LL_GPIO_SetPinMode(GPIOG, LL_GPIO_PIN_10, LL_GPIO_MODE_ALTERNATE);
 LL_GPIO_SetAFPin_8_15(GPIOG, LL_GPIO_PIN_10, LL_GPIO_AF_5);
 LL_GPIO_SetPinSpeed(GPIOG, LL_GPIO_PIN_10, LL_GPIO_SPEED_FREQ_HIGH);
 LL_GPIO_SetPinPull(GPIOG, LL_GPIO_PIN_10, LL_GPIO_PULL_DOWN);
 LL_GPIO_SetPinOutputType(GPIOG,LL_GPIO_PIN_10,LL_GPIO_OUTPUT_PUSHPULL);

But I don't see any activity on NSS pin...

What I am doing wrong ?

[Linas L]

I am very close, I can get single tranfer to DAC with correct timings and no software management, but still need to figure out how to re-trigger this with for DMA

 spi_initstruct.BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV128;
 spi_initstruct.TransferDirection = LL_SPI_SIMPLEX_TX;
 spi_initstruct.ClockPhase = LL_SPI_PHASE_1EDGE;
 spi_initstruct.ClockPolarity = LL_SPI_POLARITY_LOW;
 spi_initstruct.BitOrder = LL_SPI_MSB_FIRST;
 spi_initstruct.DataWidth = LL_SPI_DATAWIDTH_16BIT;
 spi_initstruct.NSS = LL_SPI_NSS_HARD_OUTPUT;
 spi_initstruct.CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
 spi_initstruct.Mode = LL_SPI_MODE_MASTER;
 
 LL_SPI_Init(SPI1, &spi_initstruct);
 
 LL_SPI_SetNSSPolarity(SPI1,LL_SPI_NSS_POLARITY_LOW);
 
 LL_SPI_EnableDMAReq_TX(SPI1);

After this I do DMA stuff

 LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1);
 
 NVIC_SetPriority(DMA1_Stream7_IRQn, 0);
 NVIC_EnableIRQ(DMA1_Stream7_IRQn);
 LL_DMA_ConfigTransfer(DMA1,LL_DMA_STREAM_7,LL_DMA_DIRECTION_MEMORY_TO_PERIPH | LL_DMA_PRIORITY_MEDIUM | LL_DMA_MODE_NORMAL |LL_DMA_PERIPH_NOINCREMENT | LL_DMA_PERIPH_NOINCREMENT |LL_DMA_PDATAALIGN_HALFWORD | LL_DMA_MDATAALIGN_HALFWORD);
 LL_DMA_ConfigAddresses(DMA1,LL_DMA_STREAM_7,0x24000000, (uint32_t) &(SPI1->TXDR),LL_DMA_GetDataTransferDirection(DMA1, LL_DMA_STREAM_7));
 
 LL_DMA_SetDataLength(DMA1, LL_DMA_STREAM_7, 1);
 LL_DMA_SetPeriphRequest(DMA1, LL_DMA_STREAM_7, LL_DMAMUX1_REQ_SPI1_TX);
 LL_SPI_SetTransferSize(SPI1,1);
 LL_SPI_SetMasterSSIdleness(SPI1,2);
 LL_SPI_SetInterDataIdleness(SPI1,2);
 
 LL_DMA_EnableIT_TC(DMA1, LL_DMA_STREAM_7);
 LL_DMA_EnableIT_TE(DMA1, LL_DMA_STREAM_7);

And when I trigger DMA:

 LL_SPI_Enable(SPI1);
 LL_DMA_EnableStream(DMA1, LL_DMA_STREAM_7);
 LL_SPI_StartMasterTransfer(SPI1);

[Piranha]

The first/main answer perfectly shows the uselessness of the LL drivers. And the reason is that there is no abstraction at all!