[bug report] SPDIFRX divider error

[Nixz]

Posted on October 14, 2016 at 10:43

Hi All,

I've discovered that code generated with STM32 CubeMX for SPDIFRX is faulty. SPDIFRX has dedicated PLL divider which has 2 bits (0=1/2, 1=1/4, 2=1/6 or 3=1/8), however code generates uses 4 defines which have 2, 4, 6 and 8 values. Those values are truncated to 2 bits which makes that you can select only 2 dividers:

selected 1/2 (2) becomes 1/6 (2)

selected 1/4 (4) becomes 1/2 (0)

selected 1/6 (6) becomes 1/6 (2)

selected 1/8 (8) becomes 1/2 (0)

This is a $%^%$♯ frustrating because hou have to correct this after EACH code generations. I've checked this on F746 and F767 with same results!

regards

Miko?aj Tutak

#!stm32-!cubemx-!bug-!pll-!clock

[Nesrine M_O]

Posted on October 14, 2016 at 12:02

Hi Mikołaj Tutak,

Thank you for your feedback. The issue has been reported internally.

-Syrine-

[Sirma Siang]

Posted on January 06, 2017 at 16:47

Hi Mikołaj Tutak,

First I want to thank you for your feedback.

I check your symptoms by using CueMX 4.18 + Firmware package for F7 family version 1.5.1.

I creates new project with F746 and F767, and the field you are mentionning PeriphClkInitStruct.PLLI2S.PLLI2SP is defined as uint32.

I do not see where the cast to 2 bits is done.

Could you please elaborate a bit more, and show me where do you see it ?

Great thanks in advance for your advices.

KR

Sirma