Question
BUG in RM0394 Rev 4, regarding timer (TIM2) synchronization.
When trying to synchronize (cascade) timers, specifically wanting TIM1 to provide clock for the TIM2, there is a bug in the reference manual RM0394 Rev 4.
The bug is in the recipe in the section 27.3.19, page 857, called Using one timer as prescaler for another timer, point 2.:
"2. To connect the TRGO output of TIMy to TIMz, TIMz must be configured in slave mode
using ITR2 as internal trigger. You select this through the TS bits in the TIMz_SMCR
register (writing TS=010)."
Instead of using internal trigger 2 (ITR2) as stated above, the user should use internal trigger 0 (ITR0), as stated in the Table 136 on the page 867. Moreover, there is no Internal Trigger 2 option for the TIM2/TIM3.
Sincerely,
Michal Matejasko
