Best way to sequence ADC (a lot) without DMA

[Konami]

Hi all, I'm building an application which needs to sample 8 ADC channels at roughly 10kHz, while listening for messages over SPI. The issue I'm facing is that neither of these can be missed, and sometimes they occur simultaneously. Ideally both of these use cases would use a DMA, however, the G070 I'm developing on only has 1 DMA.

Usually the SPI transfers are short enough that I could in theory fit them in the 80us or so that I have available between ADC sequencing, however this would impose a huge limitation on the comms and could cause problems down the line if we needed to support longer SPI transfers.

In light of this I'm trying to figure out the best way to sample the ADC without using the DMA. I was thinking of continuing to use the sequencer, and just handle the EOC IRQ at highest priority but I was curious to see if there are other suggestions.

[TDK]

> Ideally both of these use cases would use a DMA, however, the G070 I'm developing on only has 1 DMA.

Although it only has a single DMA, that DMA has 8 different streams. You can use one for the ADC and one/two others for the SPI. That's the easiest solution.

[Konami]

As far as I understand it, the DMA channels are muxed and therefore cannot be operating simultaneously. Am I misunderstanding this? If so that would be great.

In my use case, I might have a SPI transfer that takes 0.5ms (of continuous operation) to complete, during which the ADC DMA would need to have run 5 times. Is this possible?

[TDK]

DMA channels are muxed, only one at a time. DMA streams are not muxed. You can have ADC and SPI on the same DMA and it will operate flawlessly since you are nowhere near the bandwidth limit of the DMA.

There are details here that I'm glossing over, but the takeaway is that you can run ADC and SPI (and other stuff) on the same DMA flawlessly, provided they are on different streams, and provided you're not near the bandwidth limit.

[Konami]

Well this is great news.. I still don't fully understand how that works, but in that case I will dig into this a bit deeper. I guess this means that between copying consecutives two SPI->DRs it can hop over to copying one of the converted ADC values and then return before the next SPI data is ready?

[S.Ma]

Streams behaviour are like each one having its own dma. You probably need 2 for spi tx and rx, and per adc block. Of course, as there is one data bus, simultaneous request will be queued one memory access cycle at a time, which is way faster than any sw implementation.