Best way to combine reset signals for STM32

[Coratron]

Posted on October 14, 2017 at 04:48

Hi,

I have a design that has two STM32s in it, for this application I would like them to be able to reset each other. On top of that, there would be the physical reset button and the SWD reset signal.

What is the 'standard' solution? I have looked into OR gates, reset supervisor ICs with manual trigger, and analog switches.

I am aware the NRST pin uses CMOS.

Turvey.Clive.002

‌ , if you see this post you probably have the right answer as you have advised in a couple of posts to be careful not to use other push-pull drivers

https://community.st.com/0D50X00009XkdumSAB

 :

You don't want any other push-pull drivers on the pin, the pin should have it's own pull-up.

Another potential issue would be the continuous 'ping-pong' reset between the two STM32s, but the datasheets specifies the following:

In order to improve the consumption under reset, the I/Os state under and after reset is “analog state� (the I/O schmitt trigger is disable). In addition, the internal reset pull-up is deactivated when the reset source is internal.

So this does not seem to be an issue, but if there's a caveat, please chime in.

Thanks!

#reset-between-microcontrollers #reset #rst-on-stm32 #nrst

[Tesla DeLorean]

Posted on October 14, 2017 at 16:23

The issue being more one of using Open-Collector/Drain than being CMOS, the NRESET/NRST being considered bi-directional in most ARM implementations.

If you connect the STM32 to the same NRST net, then both will reset together. This would be an issue for Watchdog or Software Reset, as these will drive the pin low.

One mechanism would be to have two NRST nets, and connect the NRST on one to an available GPIO on another. There are also some POR chips that have a 'button' input, these could be used in a cross connected fashion. I tend to prefer the external POR as the clamping time for NRST is significantly long (100's of ms), this can be helpful with slow ramping supplies, or systems with multiple supply rails.

[Tesla DeLorean]

Posted on October 14, 2017 at 16:24

http://www.st.com/content/ccc/resource/technical/document/technical_note/group0/f4/51/bd/00/ee/cb/4d/ad/DM00067262/files/DM00067262.pdf/jcr:content/translations/en.DM00067262.pdf

 

[Coratron]

Posted on October 15, 2017 at 13:49

Thanks for replying! Both STM32s were going to drive each other's NRST with a dedicated GPIO as you pointed out, and each STM32 would have its own JTAG as well so no NRST net is shared... the main concern is if there would be a problem by doing a combination like the following:

Reset signal from JTAG                         ------- |

Reset signal from Button                       ------- |     OR Gate     |  ------ NRST pin of 2nd STM32

Reset signal from 1st STM32 (GPIO)    ------- |

Same idea for the other uC. I wonder if a resistance of 100 ohms in series with each of the input signals would do the trick instead of an OR gate. But again, I am trying to avoid headaches while debugging... messing around with the reset signal like that could be a problem.

the NRESET/NRST being considered bi-directional in most ARM implementations.

This worries me. Why would it be the case? When would it be used as an output from the uC?