Bare metal STM32F767 proper powering

[hashtala]

Hello

This is my first time soldering a MCU on a custom PCB.

As you know, STM32f767 is a very complicated chip and requires Vdd and Vss on many pins. Datasheet also states that capacitors are mandatory on each Vdd or Vref+. However Vref and Vdd (marked on figure) are neighbors and I was wondering if I can use one capacitor for both of them.

Could you also tell me if this is a proper way of placing capacitors ? Max distance from Vdd line and cap is 8mm.

As you can see, there is only one track and its obviously Vdd line.

Of course I am not done with placing all caps and tracking Vdds to pins. I first need to know if this kind of principle is going to work

 

[hashtala]

I tried to add images but I guess I do not have permissions yet

[TDK]

Your images show up.

You will find many different opinions on how to place decoupling caps. In general, the closer the better.

Using the same cap for VREF+/VDDA seems fine, unless you want to really optimize ADC noise performance.

Take a look at ST's own layouts to see how they do things. Here's an example from a Nucleo board so you can see how far the decoupling caps are. Some boards out there have decoupling caps way farther away than this--maybe 1cm or so, and yet the board works fine. It really depends how you're using things.

[Piranha]

It should be noted that the shown physical layout of PCB traces is pretty wrong!

https://electronics.stackexchange.com/questions/74509/how-to-place-decoupling-capacitor-in-four-layer-pcb

[hashtala]

thanks for letting me know that.

However, since I am using only single layer and rails are very thick and rather straight, I dont think it will have that much inductance and resistance.

For time being. I will go with this layout. However, if it does not work I will try to do what was suggested. I will post feedback