Backup SRAM for persistent RAM
I am using an STM32F4 for a project that undergoes in-field upgrade. The upgrade involves a soft reset, but I would like to back-up some critical data that will ‘persist’ through the upgrade.
Since the data that needs to persist is updated at least once a second, I would like to use persistent RAM (rather than Flash). I was considering using the Backup SRAM described in RM0090 section “5.1.2 Battery backup domain�? for this purpose.
Assuming I have all access to this memory occur within the same thread, are there any concerns with using Backup SRAM in this way.
e.g. Is there an issue with writing to this memory many times a second by executing the code below?
</p>
// Enable Power clock
</p>
__PWR_CLK_ENABLE();
// Enable access to Backup domain
HAL_PWR_EnableBkUpAccess();
{
uint32_t u32NVData = GEtTestData();
RTCWriteNVDataWord(0, u32NVData);
}
__PWR_CLK_ENABLE();
// Enable access to Backup domain
HAL_PWR_EnableBkUpAccess();
Note: I do not have a battery to power this RAM. Losing contents upon power-down is acceptable.
