backup SRAM (available in the lowest-power modes)

[2217335612]

The backup SRAM cannot be accessed in the (normal) Run mode ?

[Danish1]

You don't say which stm32 you're interested in; different ones have different features. Some only have the few words of RAM that are part of the real-time clock retained in lowest-power modes; others have more.

An important issue is that during power-up and power-down, it might happen that the processor behaves abnormally, possibly trying to overwrite the backup SRAM that you spent many microamp-hours protecting when there was no power. To make this less likely, there is generally a special write-enable bit somewhere e.g. the DBP bit in PWR->CR. Unless/until you activate the write-enable, you can't write to this SRAM. Oh and do remember to disable it once you've finished your intentional writes, to minimise the risk of accidental overwriting during during power-up and power-down.

Hope this helps, otherwise please reply explaining further your problem,

Danish

[2217335612]

Thank you very much, Danish.

The microprocessor I am interested in is the stm32h7 value line.