automatic NSS sync with SPI used with DMA

[4316139955_stm1]

Posted on December 28, 2008 at 20:13

automatic NSS sync with SPI used with DMA

[i239955_st]

Posted on May 17, 2011 at 12:36

Hi,

Is there any news with this issue ?

I'd like to use DMA to tranfer massive data to DAC with automatic chip select managment. This feature works on atmel, why this seems not to be available on much complex STM32 ? bad news for my project.

I think a workaround could be to synchronize a timer to automatically valid each SPI frame. What do you think : is it risky ? What a pity to be constrained to do that...

[4316139955_stm1]

Posted on May 17, 2011 at 12:36

Hello,

I am using the STM32 to communicate with a 8 channel, 12 bit, SPI DAC TLV5610.

The data are transmitted in Master mode with 16 bits per channel (index << 12 & value). After each word of 16 bit transmitted, the DAC internal shifter must be reseted by a falling edge on the NSS pin.

I must send the 8 channels with a sampling rate of about 10 kHz. It is why I need to use the DMA (I need to do a lot of other control calculation beside this).

For a graphical representation, see my attachment or the DAC datasheet:

http://www.ti.com/lit/gpn/tlv5610

I was not able to configure de SPI with hardware NSS and this kind of signal generation.

Is it possible to use the STM32 with this DAC and DMA ?

Or do I need to change my design, use an other DAC (but other seems to work the same way) or change the MCU ?

Best Regards

Marc Emery

[gdp123a]

Posted on May 17, 2011 at 12:36

From my reading of the manuals (I haven't tried this, so someone please correct me if I'm wrong). You should be able to use one of the timers to trigger the DMA from memory to the SPI. The same timer should hopefully be able to be programmed to output a pulse for the CS line.

For those SPI chips that are in sleep mode when CS is high, this is probably a superior way of controlling CS (possible power savings).

Assuming the above is possible, there is a problem if your only clock source is a 32 KHz crystal. Then the timers can only be synchronised to the HSI - which might be a problem for producing accurate waveforms etc.

I use DMA to a small LCD via the SPI, but the DMA trigger is the SPI buffer empty signal. I send about a 100? bytes at a time. Ideally there should be a CS signal for every byte, but I have found that it works fine if I manually put CS before the start of the transfer and keep it low until the transfer finishes.

I have noticed that for some chips the CS needs to be low for a minimum of 10 nanoseconds before the first rising clock edge ie. not very long. If the SPI clock signal remains high between transfers (I can't remember and my hardware is out of action for the moment) - then I wonder if the CS signal could be derived from the clock signal (the first falling edge) using a schottkey diode plus resistor and capacitor? Just a thought - probably too risky to put in any proper design.