Atomic increment/decrement usint IAR EWARM

[johnspeth9]

Posted on October 20, 2009 at 16:54

Atomic increment/decrement usint IAR EWARM

[johnspeth9]

Posted on May 17, 2011 at 13:27

Can anyone give me some hints about how to accomplish an atomic integer increment and decrement operation so that interrupts don't need to be disabled while the integer is changing?

I'm using IAR EWARM 5.4. Straightforward and also clever non-typical strategies are welcom.

Thanks, John Speth

[clive2]

Posted on May 17, 2011 at 13:27

The Load/Store architecture doesn't permit atomic R-M-W operations.

An alternative may be to look at the atomic bit level manipulations.

http://www.arm.com/products/CPUs/ARM_Cortex-M3.html

Depending on you use pattern, you might be able to acquire a global spinlock, perform the addition (subtraction,increment,decrement,swap,..), and release. While admittedly this might be a problem for you if you need the inc/dec in some interrupt code, a simple thread safe implementation should be possible.

-Clive

[picguy]

Posted on May 17, 2011 at 13:27

Sorry, there is no atomic increment / decrement.

There are two ways around your problem. But because you are asking, method 2 may be your best bet. Method 1: Look long and hard at LDREX and STREX.

Method 2 involves changing the problem into something that works without interlocks on a RISC processor.

I had the same problem. In my little multitasking OS on the 8085 & x86 I used a byte that was the number of unprocessed timer ticks. The ISR incremented the byte and if the byte was non-zero the timer part of my OS decremented the byte. I had the problem you had. How to use a single element on a RISC machine like ARM and not get messed up.

I changed the way I did things. I now increment ISR_timer in my timer ISR. My OS timer function compares OS_timer & ISR_timer. If not equal I OS_timer++ and then do my millisecond tick stuff.

[clive2]

Posted on May 17, 2011 at 13:27

While I understand the premise, I couldn't find any command line option or #pragma that would do that with ARMCC. The other bigger problem would be pre-compiled libraries.

-Clive

[johnspeth9]

Posted on May 17, 2011 at 13:27

Thanks, guys. Your answers match those that I received from IAR: no direct atomic inc and dec.

However, I had one idea I've seen in other compilers but not IARs. This compiler allowed the programmer to remove one or more registers (as in Rn) from the working set of registers the compiler uses for scratchpad use. If I can sequester a register from the compiler, then I can have my exclusive and atomic value. Does anyone know if that's possible?

John Speth