Am I getting accurate results from the IBIS models? Is a rise time of 160 ps realistic for a GPIO at 1.8 V?

[shffhsdfhse]

I'm doing some signal integrity verifications using the STM32H7 IBIS models to determine if I need terminations for connecting my STM32H7 to a HyperRAM memory.

I was a bit surprised with the poor signal integrity I was getting, which I assumed was due to faster edges than expected. I looked a bit deeper in my simulations and noticed that the rise time for the IO was only 160 ps. This is an extremely fast number and I was expecting it to be closer to 1 ns.

The IO is running at 1.8 V with HSLV enabled and the fastest IO speed. The MCU has the UFBGA176+25 package.

Is this 160 ps number realistic?

[LCE]

I'd say no, not even in a perfect world without stray capacitance from PCB routing and no load.

But that's just an experienced guess.

Datasheet says at highest speed:

Output high to low level

fall time and output low

to high level rise time

C=10 pF, 1.62 V≤VDD≤2.7 V(4) - 1.9 ns

So maybe your simulation is closer to the truth than I thought - if you don't have any load capacitance in your sim.

[shffhsdfhse]

I might actually be having some issue with the simulation tool.

I'm getting essentially identical results when using the io8_hslv_ft_hs_1v8 (high-speed hslv) model vs the io8_hslv_ft_ls_1v8 (low-speed hslv) models.

Same thing when using io8_ft_hs_1v8 (high-speed non-hslv) model vs the io8_ft_ls_1v8 (low-speed non-hslv).

The only difference I seem to get is when I enable/disable hslv.