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Skfir
Associate III
November 26, 2022
Solved

ADC1 data format? Nucleo-u575 board

  • November 26, 2022
  • 6 replies
  • 1273 views

Hi everybody! Could please someone enlighten me on the data output format of the ADC1, on regular channels without oversampling, everything is set to default values? Just enabled one channel and converted it. The thing is, I use 2.5v internal reference, when I connect the input to GND, after conversion I get 0x3FFF, but when the input is connected to +3.3v, the data register reads zero. So please if someone could explain what is the data format and why do I get such interesting values.

Thank you!

This topic has been closed for replies.
Best answer by Skfir

Figured out what was the cause of the problem. The point is, ADC1 requires its clock to be in 5Mhz-55Mhz range. In my case HCLK was 160Mhz and accidentally I was writing ADC1 clock division bits one line before I enabled the whole business in the RCC_AHB2ENR1 register, so the division bits never got written. Silly me. Glad it all works now! Thank you guyz!

6 replies

waclawek.jan
Super User
November 26, 2022

Which STM32?

> The thing is, I use 2.5v internal reference

How?

JW

S.Ma
Principal
November 26, 2022

There are many different adc variations across the STM32 portfolio. The ones capable of differential mode can probably be configured to what you observe....

Skfir
SkfirAuthor
Associate III
November 26, 2022

Oh sorry, forgot to mention, i use NUCLEO-U575 board and dont play with data format, i only power the ADC1 one up, set one channel up and see what values the ADC1 gives. On that board, the ADC1 channels certainly can be configured in differential mode, but i didnt do that. What actually surprises me is the fact, that +3.3v shows zero and GND gives 0x3FFF

S.Ma
Principal
November 26, 2022

Best way to learn, go debug mode after stopping a basic code. Use adc and gpio hw register view and edit them manually until it does what you want.

You can keep a pin floating and use the selectable internal pull up xor down to play with the adc.

Skfir
SkfirAuthor
Associate III
November 26, 2022

Will do that. Thank you . !

Skfir
SkfirAuthorBest answer
Associate III
November 27, 2022

Figured out what was the cause of the problem. The point is, ADC1 requires its clock to be in 5Mhz-55Mhz range. In my case HCLK was 160Mhz and accidentally I was writing ADC1 clock division bits one line before I enabled the whole business in the RCC_AHB2ENR1 register, so the division bits never got written. Silly me. Glad it all works now! Thank you guyz!