ADC Sample Time Selection

[geoffreymbrown]

Posted on April 10, 2012 at 22:18

While it is clear how to configure the ADC sample time, the documentation doesn't provide insight into why one might prefer 239.5 cycles over 13.5 cycles, or the impact of selecting 7.5 cycles (I'm guessing 6 bits of accuracy).

I do understand the sampling theorem so I know why one might choose a sampling rate.  What I'm unclear about is the effect of setting a particular sampling time for the STM32.

Is this documented somewhere ?

Geoffrey

[raptorhal2]

Posted on April 10, 2012 at 22:55

Yes. See application note AN2834 .....Best ADC Accuracy...  Section 1.2.5.

In summary, the ADC sample and hold input behaves like an RC circuit. Depending on the signal impedance, the sampling time needs to be adequate to get the sample and hold capacitor charged up to within 1 LSB of the signal voltage.

Cheers, Hal

[geoffreymbrown]

Posted on April 15, 2012 at 01:53

Thanks, that app note is a help.  Also, I finally found the note in the reference manual that made it clear that the configuration is for the sample time -- conversion time is fixed number of cycles.  So 1.5 is a sample time of 1.5 cycles and so forth.   

Geoffrey