ADC's EOC event

[icuic]

Posted on November 19, 2012 at 13:29

Hello, everyone!

I have a question about ADC's EOC event, when is this bit been set?

For example,there are 6 ADC channels in my program.

Is it right as bellow:

A channel converted--EOC--B channel converted--EOC...F channel converted--EOC

or

A channel converted--B channel converted--...F channel converted--EOC

Thanks!

#adc-eoc #adc-eoc #adc-eoc #read-the-correct-f***-manual

[Tesla DeLorean]

Posted on November 19, 2012 at 16:25

For multiple channels I think you're expected to use DMA, and the TC/HT interrupts to get your latter scenario.

[frankmeyer9]

Posted on November 19, 2012 at 19:18

I have a question about ADC's EOC event, when is this bit been set?

 

On End-Of-Conversion for every single channel.

That means, 6 times in your example.

As clive suggested, it is advised to use DMA if you convert more channels, or often, or both.

[icuic]

Posted on November 20, 2012 at 02:16

11.3.10 Discontinuous mode

Regular group

This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to

convert a short sequence of n conversions (n <=8) which is a part of the sequence of

conversions selected in the ADC_SQRx registers. The value of n is specified by writing to

the DISCNUM[2:0] bits in the ADC_CR1 register.

When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx

registers until all the conversions in the sequence are done. The total sequence length is

defined by the L[3:0] bits in the ADC_SQR1 register.

Example:

n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10

1st trigger: sequence converted 0, 1, 2

2nd trigger: sequence converted 3, 6, 7

3rd trigger: sequence converted 9, 10 and an EOC event generated

4th trigger: sequence converted 0, 1, 2

The paragraph above is quoted from Reference Manual(RM0008).Please take a attention about that bold sentence, How can i understand that sentence？In this sequence,there is only one EOC event generated.

[frankmeyer9]

Posted on November 20, 2012 at 08:05

I referred to:

11.3.4 Single conversion mode

 

...

 

Once the conversion of the selected channel is complete:

 

If a regular channel was converted:

 

– The converted data is stored in the 16-bit ADC_DR register

 

– The EOC (End Of Conversion) flag is set

 

 

11.3.5 Continuous conversion mode

 

...

 

After each conversion:

 

If a regular channel was converted:

 

– The converted data is stored in the 16-bit ADC_DR register

 

– The EOC (End Of Conversion) flag is set

 

Cited from the same document.

Not sure how to comprehend this Discontinuous Mode, since the ADC has just one result register. Maybe the DMA relies on something else than EOC.

[marcin]

Posted on September 13, 2015 at 16:49

As we might logically think the EOC interrupt should occur after each channel succesfull conversion. Unfortunetlly it doesn't work it such a way. It took me a while to discover, it's acctually a crap. The interrrupt is generated ''only'' and''only'' when it finished to convert all of the channels. Natural consequences is that all of the data in DR register are overwritten, so what you going to get in EOC interrupt handler task is the result of last conversation. For me it's a terrible bug!!! It should work the following way:

1. Fire up the ADC conversation

2. It creates EOC interrupt after each channel succefull

3. Because it's discontinues mode it should stop itself when all of the channels are scaned.

Like I said, crap. 

[raptorhal2]

Posted on September 13, 2015 at 23:54

lee.stanley's quote is probably from RM0041 Rev 4 for the F100 series. For F101's and up, RM0008 Rev 15 currently applies, and states an EOC for each channel conversion.

So which chip do you have ?

Cheers, Hal