About STMF407xx I2S DMA circular buffer playback DMA interrupt inconsistency issue
The STM32F407XX chip is used in the project, and the audio codec chip WM8978 is connected through I2S. The voice data adopts 8000 sampling rate data format 16bit, two-channel. STM32 I2S unidirectionally writes audio PCM data, using cyclic DMA double buffer writing, sub-packet left and right channel 64 bytes (stero), one packet is written once, and the time interval between packets is 2ms after startup (total data volume 8000x16x2/8= 32000 bytes), most of the DMA interrupts generated are 98% at intervals of 2ms, but 50us interrupts are generated occasionally, and there are also occasional interruptions greater than 2.5ms. The total playback data packets in 10s statistics are more than 50 packets, which are about 1s. 4 to 5 packets appear abnormally. The theory should be 500 packs, but the actual consumption is 504+ packs, which leads to the matching of the collected samples and the playback samples, resulting in squeaking noise. May I ask whether the cyclic DMA buffer should be the 2ms interval of the playback sampling rate, that is, the business requirement, and the interrupt should be the same period/frequency? How to troubleshoot?