About PRI_N field of "System handler priority registers" in Cortex M4 processors.

[JGarc.9]

In page 233 of document PM0214 says

Each PRI_N field is 8 bits wide, but the processor implements only bits[7:3] of each field, and bits[3:0] read as zero and ignore writes (where M=4).

But there is a mistake, it couldn't be bits[7:3] and bits[3:0] at same time in that statement. Is the implemented bits[7:4]?

[JGarc.9]

Right now, I have figured out that, in each register the bits PRI_N[3:0] are read only, and PRI_N[7:4] are r/w. So the implemented bits are bits[7:4].