About FMC-SRAM transmission
hi ，I have some problms about FMC-SRAM with own r&d board based on stm32h750，hope someone give me some hlps�?
Now we have a strange problem that we operate on an external 16-bit bus. If we just write a word (16-bit) that is 2 bytes, the actual bus operation is to write 8 bytes (64 bits) in a row.And it's aligned with an 8-byte address.
That is, write one of the four 16-bit words in the 8-byte segment (16 bits) and the bus will write the four 16-bit words together.(we confirmed this by testing the waveform and observing the actual data.) But if you are reading a word (16 bits) of the external bus data is a single read cycle of the external 16-bit bus, unlike the write process which is 4 cycles.
I don't know how to modify or set this mode.
Please hlp to guide, thx!
Here's some code about FMC.
*FMC_BCR1_Address=0x80201057;
/* bit31: 0x01 FMC_EN; bit21: 0x01 WfifoDIS ; bit14: 0x00 disable EXTMOD ;bit12: 0x01 Write enable; bit6: 0x01 FACC_EN; bits5-4: 0x01 WIDTH 16bits; bits3-2: 0x01 PSRAM ,00:SRAM,01:PSRAM(CRAM),10:NOR Flash/OneNAND Flash; bit1: 0x01 MUX_EN ; bit0: 0x01 MBK_EN */
*FMC_BTR1_Address=0x3FF10424;
/*bits3-0: 0x02 ADDSET cycle; bits7-4: 0x01 ADDHLD cycle; bits15-8: 0x04 DATAST cycle; bits19-16: 0x01 BUSTURN cycle; */