48MHz clock source selection, not necessarily 48MHz?
I have (another) dumb question... but I learn so much from my dumb questions, so bear with me.
On our STM32F7, we are using a couple of peripherals that use the PLL48CLK. I see from [RM0410, Figure 13 page 153/1954] that this is selectable as the output of PLL or PLLSAI via the DKCFGR2.CK48SEL bit.
Upstream of those, are configurable parameters, namely the Q divisor in the PLL and the P divisor in the PLLSAI.
This is a little confusing to me, since this signal is called throughout the datasheet, the "48MHz clock". Well, it's not necessarily 48MHz, I suppose, if I modify those P and Q values.
So which is the case, is it (a) I *need* to configure P and/or Q (and upstream settings) so that the result is a 48MHz clock, or things won't work? or (b) is "48MHz clock"/"PLL48CLK" just a nickname of sorts, a guideline, and I can set this to anything I want in actuality and the downstream peripherals will still work, although faster or slower?
Or, sadly, (c) I completely misunderstand everything.
Thanks very much.
