2 PWMs to control full bridge converter

[david]

Posted on May 07, 2013 at 13:27

Is there an easy way to get the TIM1 in a

STM32F303 to ouput two complemetary signals (TIM1_CH1 and TIM1_CH1N) with a 20% duty cycle for both signals?

If I output 20% duty for TIM1_CH1, the complementary, TIM1_CH1N, always gets the inverse of the first (80%). I would like to have both signals at 20% duty.

The problem we want to solve is to have two signals which are never high at the same time (that is why we thought the complementary outputs would be good) with a deadtime between them and a configurable duty cycle 0<dutycycle<50% for both.

In the attached image I've got an example of how I would like the PWMs to behave. This is using the TIM1_CH1 and TIM1_CH1N outputs but I've used the deadtime to  get two different dutycycles and I would like to accomplish the same thing without having to modify the deadtime for every change of duty cycle. Is there a way to do this?

#pwm #stm32-pwm-timers #tim1

[jj2]

Posted on May 09, 2013 at 06:02

If you're sure to program-in adequate dead time - would not the insertion of a single inverting gate - w/that gate fed by, ''TIM1_CH1N'' - be a quick/easy solution? 

Such gates are available in small - SOT23-5 package (single channel) or you can choose an soic which holds 6 such inverting channels. 

When power circuits are, ''in play'' - the added cost/size of such buffer inverters may be justified by the protection they provide to the MCU along with extra current source/sinking...

[david]

Posted on May 16, 2013 at 08:30

I'm not sure I understand you correctly but would this give me individually controllable duty cycles for the two signals?

[zzdz2]

Posted on May 16, 2013 at 10:49

I think you could try two channels and center-aligned PWM mode.

To me it looks like general purpose timer would do it with 2 channels.

[david]

Posted on May 20, 2013 at 08:08

Yes, you're right and that's how I've implemented it.

It's just that I wanted to have the hardware make sure I could never have the two PWMs high at the same time. Now I don't have that. As it is now, as long as I never write a duty higher than 50% there's no problem but if for some reason the two duty registers gets set to 60% we will have quite a spectacular hardware failure...

My first idea was therefore to use the complementary outputs to guarantee that the two outputs never was set high at the same time.