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John Hite
John Hite
Associate III
March 24, 2017
Question

18.4.17 TIMx DMA control register (TIMx_DCR)

  • March 24, 2017
  • 1 reply
  • 687 views
Posted on March 24, 2017 at 19:02

in RM0090 18.4.17 TIMx DMA control register (TIMx_DCR) it states:

Bits 4:0 DBA[4:0]: DMA base address

This 5-bit vector defines the base-address for DMA transfers (when read/write access are

done through the TIMx_DMAR address). DBA is defined as an offset starting from the

address of the TIMx_CR1 register.

Example:

00000: TIMx_CR1,

00001: TIMx_CR2,

00010: TIMx_SMCR,

...

Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this

case the transfer is done to/from 7 registers starting from the TIMx_CR1 address.

Does this mean the transfers are overwriting the timer control registers?

jh

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    1 reply

    Khouloud GARSI
    Khouloud GARSI
    Technical Moderator
    March 30, 2017
    Posted on March 30, 2017 at 18:48

    Hi

    Hite.John

    ,

    The main usage of thetimer DMA-burst feature is to update the content of multiple registers of the timer peripheral each time a given timer event is triggered.

    In the example cited in the reference manual, yes, theTIMx_CR1 and the 6 following registers will be overwritten.

    I advise you to have a look at section 5.2.Timer DMA-burst feature in the application note

    http://www.st.com/content/ccc/resource/technical/document/application_note/group0/91/01/84/3f/7c/67/41/3f/DM00236305/files/DM00236pdf/jcr:content/translations/en.DM00236pdf

    .

    Khouloud.

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