How to enable the timer channels to follow the correct PWM Schemes

[BoboyeOkeya]

Hi All,

Can anyone help me decipher exactly what is going on in this piece of code. It is meant to be a H-PWM,L-ON scheme meaning at any hall status step, the high side switch of one leg of my inverter is pulsed while the low side switch of the other leg of my inverter is just switched. This is shown in the first picture under case1,case2,...,case6

Now, this would mean that I only need to enable the timer (in this case timer 1) channel that corresponds to the high side switch of one leg and the low side switch of the other leg while disabling the remaining switches. This is shown in second picture under the functions MC_Core_LL_EnableChannelsHfPwmsStep1(uint32_t *pHfTimer) etc.

The main reason I needed to figure this out is that I am trying to implement other PWM schemes as shown in the third picture. But the code does not respond.

Apparently, the channel enabling is meant to be done by adjusting the CCER, but based on this code it is just not rightly adjusted but it works. It is a 16bit timer and I am using the STM32F031C6TX.

My overall point: I would really appreciate some help on how to properly enable the right channels. For example, in step 1, it does not make any sense as to why a channel (CH2) and its complementary channel (CH2N) should be enabled at the same time in the software. But on checking the actual pulses on the inverter legs, they are never enabled at the same time because that would make that leg short-circuit current to ground.

P.S: I am not an embedded software guy, just an electronics guy trying to graduate loool.

 

[waclawek.jan]

There are no pictures in your post.

Please note that salesforce used here instead of proper forum software does not correctly handle copy/pasted pictures; you need to upload them - click on the "image" icon below the edit windows.

JW

[BoboyeOkeya]

Hi Jan,

Yes that is very correct.

I made the adjustment already.

[waclawek.jan]

Can you show us the waveforms corresponding to the above code?

Also read out and post the TIM registers content.

You've already read the timer chapter in RM, I presume.

JW

[BoboyeOkeya]

Yes, I have read the timer chapter, I could not understand everything but I got some parts.

Pardon, the bad measurements, but the yellow graph is a high-side gate signal to the switch of one leg, while the green graph is a low-side gate signal to the switch on another leg.

Since its H-PWM,L-ON, the high gets pulsed while the low side just stays on.

Here you go kind sir.

I zoomed in a lil bitTIM1 register readouts

[waclawek.jan]

There's little point in looking at the registers content in decimal.

> the yellow graph is a high-side gate signal to the switch of one leg, while the green graph is a low-side gate signal to the switch on another leg.

Okay so that does not tell much about the overall working.

If I understand the diagrams correctly, the phases, when high-side is PWM, and when low-side is active, are not overlapping.

I assume the legs where both CHx and CHxN are enabled, are those where the CCRx is set to 0 or equal to ARR, which means that the outputs are on a steady state. I also believe the respective polarities are set so that those two outputs won't cause "shoot through".

I have no better advice than to read that TIM chapter in RM0091 again, until it starts to make sense. Try perhaps starting with the registers description, also review the "Output control bits for complementary OCx and OCxN channels" table (its upper half is what corresponds to "normal" working; lower half is mostly "emergency stop" (Break) related.

You may want also to experiment; the complete motor control is perhaps not the best test bed, you may want to experiment with bare timers if available, to reduce risk of making any harm. Stopping the program, observing the TIM registers and the respective outputs is fun; at that moment, changing the TIM registers from debugger and observing the effect of those changes is even more fun.

JW

[BoboyeOkeya]

Hi Jan,

Thank you for your robust responses. That is true, the waveforms did not really tell much about the overall working.

Yes, the legs where both CHx and CHxN are enabled are those where the CCRx is set to 0.

I will do as you have recommended then.

I just have one question: if CCRx is set to 0 and both CHx and CHxN are enabled, and let's assume the PWM mode is PWM MoDE1.

1. Does that not mean that OCxREF would equal to 0 once counter CNT exceeds 0?
2. if that is correct, then CHx should go low while CHxN should go high?
3. if that is correct, then why would i ever need to enable both CHx and CHxN. instead of just enabling CHxN to switch on the low-side MOSFET?

[waclawek.jan]

There are three states on any given pin: 0, 1 and HiZ. Disabled means the pin is HiZ, not 0.

Read the "Output control bits..." table I've pointed to above.

(Yes you can have pulldown/pullup switched on, so there are more states than that, but you get the point).

JW

[BoboyeOkeya]

Hi Man,

I really appreciate this, you were absolutely right. The answer I needed was in the table after all this while.

I have been able to fix it, and now I have been able to implement PWM (c), (d), and (e) correctly.