Wrong RAM_D2 memory in LwIP examples for NUCLEO-H723ZG

[heveskar]

In LwIP examples for NUCLEO-H723ZG, in the linker, I think that there is an incorrect range of RAM_D2 memory.

For example here: 

MEMORY
{
 ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
 RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
 ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
 RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
 
}

SRAM available from 0x30000000 has 32 kB available

from  the reference manual:

Or am I missing something? I am writing here before creating an issue on GitHub as I am not sure I am not misreading something. I think they took it from the STM32H74x/H75x devices as those have this amount of memory.

The example works correctly as the addresses used are hard-coded in the application, but the size should be correct either way.

 

[LCE]

You are correct, the RAM size of SRAM1 & SRAM2 in D2 is 16kB each.

There are many errors in many ST files, probably the typical copy & paste.

BTW, in the H723 - H735 series, ethernet DMA can access AXI RAM, although use of descriptors (and maybe some RX/TX buffers if space allows) in D2 = SRAM1 & SRAM2 is preferred, as the ethernet MAC also resides in D2. (See block diagram RM0468, page 107)

[KDJEM.1]

Hello @heveskar ,

Thank you for reporting this issue.

I confirm the typo , it is a known issue and it is already reported internally.

Internal ticket number: 152716 (This is an internal tracking number and is not accessible or usable by customers).

Thank you for your contribution in STCommunity :).

Kaouthar

[heveskar]

Thanks.

[KDJEM.1]

Hi @heveskar ,

RAM_D2 size issue is fixed in GitHub.

Thank you for your contribution in STCommunity.

Kaouthar