while (ETH->DMABMR & ETH_DMABMR_SR) HANGS

[Terje Bøhler]

Posted on December 07, 2016 at 16:03

Hi.

This above code (part of the procedure PowerControl(..)) runs OK on my MCBSTM32C (KEIL evaluation) board.

But, when the same code is loaded to my target system, the SR-bit (Software Reset) of the ETH_DMABMR is always 1.

I can't see any problem with my HW... I see other people have questions regarding the same code. I really appreciate assistance with this issue.

best regards

Terje B�hler

#ethernet

[Imen.D]

Posted on December 09, 2016 at 10:50

Dear

[e-mail]

‌,

We need more clarification on the casethatyou are facing and more details about thedevice used and yourconfiguration.

Are you using CubeMX (which version)?Hal version ?This will helpuser forum to answer you.

Maybe you can try with working

LwIP examples available in your STM32CubeXX firmare package.

Best Regards

-Imen-

[waclawek.jan]

Posted on December 09, 2016 at 11:01

MII/RMII clock available from external source? Clock pin enabled and AF set appropriately in GPIO? All 3 clocks enabled in RCC?

JW

[Terje Bøhler]

Posted on December 13, 2016 at 14:46

Thanks Jan.

This is my first Ethernet project so my knowledge is a bit limited.

We use a KEIL Middleware 'MDK-Plus' license (on KEIL uV5 IDE), a KEIL RTE-generated SW (with Network:CORE:IPv4) which runs well on the KEIL MCBSTM32C Evaluation Board.

So, when we load/run exactly the same SW:

1) On KEIL MCBSTM32C Evaluation Board ==> SW runs perfectly well

2) On my newly developed target ==> SW hangs as descried

So, I would very much appreciate any suggestions on which parts of our HW that may be defect, that would provoke such a SW-hang-behavior.

Best Regards

Terje Bøhler

[waclawek.jan]

Posted on December 13, 2016 at 15:38

Terje,

I said it above: MII/RMII clock presence is the first to check. I don't know if you use MII or RMII - in the first case, using an oscilloscope, you should see 25MHz clock both on  MII_TX_CLK and MII_RX_CLK (PC3 and PA1); in the second, 50MHz on RMII_REF_CLK (PA1).

As far as SW is concerned, the proper mode (MII/RMII) shall be selected in SYSCFG_PMC; above pins have to be correctly configured as AF for ETH in GPIO and all 3 ETH clocks enabled in RCC (and reset released in RCC and system clock at least 50MHz)  - but if the same software works on other platform these shouldn't be the issue in question.

JW

[Terje Bøhler]

Posted on April 24, 2017 at 13:17

Thanks JW (we use RMII)

Yes, there was actually a HW-failure on our external 50MHz oscillator driving the (STM32F107's)  MCU's PA1-pin (RMII_REF_CLK) and the corresponding 'RMII REFERENCE CLOCK' signal on our Ethernet Transceiver.

Best regards

Terje Bøhler

[waclawek.jan]

Posted on April 24, 2017 at 13:23

Thanks for letting us know.

JW