What is the timing of the chip bootloader for the STM32F765?

[BStel]

We have a project using the STM32F765II and have found that we cannot consistently get into the chip boot loader. I have read through AN2606 and found that it's current version doesn't seem to have timing information for this processor. We are trying to use USART1 to load code. During the debugging, I found the STM FLASHER program and tried it only to discover that it does not wait for the code to have enough time to start up. It seems to send the 0x7F within about 1.5-2ms after grabbing the COM port. Every time with that program the chip does not respond to the first attempt to send the 0x7F likely due to the start up time of the bootloader (which is not specified in AN2606) after the NRST. We use an FTDI USB to serial chip for our COM port, and the DTR and RTS lines (through an inversion) to drive the NRST and BOOT0 pins. A consequence of doing this is that we always get a reset event when the host PC takes hold of the COM port the first time, thus the first byte going out that soon after an NRST is a problem. So, I found that if I just retry later (about 2 seconds is what we chose) that many of the targets enter the bootloader just fine and we can unlock, erase, and program as we need to do. However, since AN2606 doesn't have this processor in it I can't determine how long we should wait other than knowing empirically that a wait is necessary. Also, I assume that if we wait too long then the loop will move on to things like I2C and SPI, etc. How much time does the rest of the loop take to expire before serial detection becomes possible again?

[Tesla DeLorean]

>>However, since AN2606 doesn't have this processor in it..

F756 and F75x parts are in the Rev 37 document

https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf

Last I checked, the boot loader is looking for signal activity, using the USART RX pins into a TIM to measure the pattern.

[BStel]

Thanks for the reply. I also noticed the processor is included in the document, but only as far as section 38 where the bootloader flow is described well enough. However, this processor is conspicuously absent from section 60 of the document where timing numbers are discussed. I considered using timing numbers from the 74XXX/75XXX which is in that section as well as the 72XXX/73XXX family, but there are differences that impact not only the startup timing but the flow timing thereafter. What we need added to section 60 is the timing specific to the 76XXX family. Further although I don't use the CAN peripheral it is in the boot loader connection sensing loop and cannot possibly take 0ms to complete, it appears that the CAN peripheral sensing timing is missing from this section as well! I don't know what the overall loop takes to complete for this processor without this information.

Since we use the serial connection, that is my focus but the flowchart suggests that the processor isn't always on task for sensing the baud rate. Perhaps the diagram is misleading and the whole thing is interrupt based? If so they should put some sort of perimeter bubble around all of the peripheral detection blocks to indicate they are happening continuously, or at least indicate as much in a note of some sort. I would hope that this is indeed an interrupt based scheme such that after I wait for the boot loader startup time (whatever that may be for this processor) that the 0x7f byte can be sent by the host at any time thereafter and that the serial bootloader portion would then take over as is described in the document. Again, this is not clear.