tcpip thread message fetch is not running in lwIP if caches enabled in STM32F767

[RBG]

tcpip thread message fetch is not running in lwIP if caches enabled in STM32F767.

 /* Enable I-Cache---------------------------------------------------------*/

 SCB_EnableICache();

 /* Enable D-Cache---------------------------------------------------------*/

 SCB_EnableDCache();

[TDK]

Cache management is nontrivial. You can either disable it, or learn how to handle it properly.

https://community.st.com/s/article/FAQ-DMA-is-not-working-on-STM32H7-devices

[Piranha]

https://community.st.com/s/question/0D50X0000BOtfhnSQB/how-to-make-ethernet-and-lwip-working-on-stm32

[RBG]

Can i get the working example code with lwip.

I feel the problem is lwIP driver Rx data buffers not aligned to cache line size. The address and size of buffers, on which D-cache invalidation are used, must be aligned to __SCB_DCACHE_LINE_SIZE, which is 32 bytes for Cortex-M7.

So expecting properly aligned buffers example code for STM32F767 with lwip for the reference.