STM32H753 with FPC2534

[TienNHxz04]

I am working on a project involving communication between an STM32H753 and an FPC2534. I have successfully connected the two components, and the system works as expected; however, it stops functioning when I enable the I-cache and D-cache on the STM32H753. Could you explain why this happens?

[AScha.3]

Probably nothing about the sensor - problem is only in your software.

I-cache should only make the cpu faster, so try I on and D-cache off.

And you have set optimizer level ?  -O2 is fine.

[TDK]

You probably have a bug in your code and/or are not handling cache correctly. There is no magic 8 ball solution here. Debug, simplify the problem, analyze, etc.

[mƎALLEm]

Hello,

Are you using DMA for the transfer between STM32H753 and FPC2534?

In that case you need to ensure the data coherency by cache maintenance. Most probably the issue occurs when you enable the D-cache.

Please refer to the application note AN4839 “Level 1 cache on STM32F7 Series and STM32H7 Series” especially the section 3.2 Example for cache maintenance and data coherency

The easiest way to overcome the behavior is to disable the cachability for the transfer buffers memory address using MPU keeping the cache itself enabled for the rest of the system. 

[TienNHxz04]

I am using DMA_UART1 for communication between two components. I need to determine the cause of an error that occurs when ICACHE and DCACHE are enabled.

[mƎALLEm]

So need to ensure the cache coherency and there is no way to get the reason of the issue/behavior from the cache (I or D). So again, please refer to the application note on how to ensure the cache coherency.