STM32H723: priorities DMA: ETH vs DMA 1/2

[LCE]

Heyho,

I could not find any info about the priorities of non-DMA1/2 masters, esp. DMA 1/2 vs. ethernet DMA is important for me.

STM32H723..735

[waclawek.jan]

Unless you get some more authoritative answer, expect them to be arbitrated round-robin by the AHB matrix arbitrator (including other masters, like the AXI-AHB bridge through which processor and MDMA accesses the D2 slave lanes).

 

JW

[LCE]

Thanks for the info!

So until now I cannot influence these priorities on the AHB side, or is there something like the AXI QoS registers (quality of service = priority, AXI_INIx_READ_QOS) for the AHB?

[waclawek.jan]

IMO no.

I am not ST.

JW

[LCE]

> I am not ST.

:grinning_face_with_sweat:

But usually more helpful! :flexed_biceps: