STM32H5 and memory barriers usage in ICACHE/DCACHE APIs

[magnus]

Hello.

STM32H5
I'm used to cache operations using memory barriers (ISB/DSB), but looking at a function like HAL_ICACHE_Invalidate() or HAL_DCACHE_Invalidate() I can't find any. Are memory barriers not needed with STM32 ICACHE/DCACHE?

[Saket_Om]

Hello @magnus 

Thank you for bringing this issue to our attention.

I reported this internally.

Internal ticket number: 207571 (This is an internal tracking number and is not accessible or usable by customers).

 

[Saket_Om]

Hello @magnus 

Do you observe any functional issue with the current implementation of HAL_ICACHE_Invalidate() and HAL_DCACHE_Invalidate().