STM32F407VGT6 DMA register

[widrat]

Posted on March 05, 2013 at 12:19

Hello everyone,

at the moment I work with the STM32F407VGT6 by using the ''stm32f4x7_eth_lwip'' demo which is shared by STM. The example projectthat i tryed was ''tcp_echo_server''

My problem with all demos which are using ethernet is the  ETH_SoftwareReset(); (stm32f4x7_eth_bsp.c  row:95)

while (ETH_GetSoftwareResetStatus() == SET); (stm32f4x7_eth_bsp.c  row:95)

there he expect a sofware reset by setting the reset bit.

If i follow up to reset operations in stm32f4x7_eth.c I found the problem in the DMA register

 

void ETH_SoftwareReset(void)

 

{

 

  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */

 

  /* After reset all the registers holds their respective reset values */

 

  ETH->DMABMR |= ETH_DMABMR_SR;

 

}

 

 

 

/**

 

  * @brief  Checks whether the ETHERNET software reset bit is set or not.

 

  * @param  None

 

  * @retval The new state of DMA Bus Mode register SR bit (SET or RESET).

 

  */

 

FlagStatus ETH_GetSoftwareResetStatus(void)

 

{

 

  FlagStatus bitstatus = RESET;

 

  if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)

 

  {

 

    bitstatus = SET;

 

  }

 

  else

 

  {

 

    bitstatus = RESET;

 

  }

 

  return bitstatus;

 

}

So I look in reference manual of the STM32F4xx on page:910 28.8.4 DMA register description.

There is indicated a Reset value: 0x0000 2101 but my debuger shows me the value: 0x0002 0101.

So the result is a continuous loop.

I am desperately, someone has an idea how to fix that problem?!

thank you for your help

Jonas

#stm32f107 #ethernet

[Tesla DeLorean]

Posted on March 05, 2013 at 12:37

Looping issues related the Ethernet peripheral tend to revolve around the clocks (enabled vs not), and the MAC/PHY.

Is the software being used on the board it was designed for, or something else?

[widrat]

Posted on March 05, 2013 at 12:57

The Software was for the STM32F4x7 line.

But this example was listed by examples for STM32F407VG. 

I can't find any other example-projects for ethernet. It must be the right.

[waclawek.jan]

Posted on March 05, 2013 at 14:00

> There is indicated a Reset value: 0x0000 2101 but my debuger shows me the value: 0x0002 0101.

This is a typo in the manual. There are dozens of them.

Nevertheless, you problem is, that the reset bit (bit 0 of that register) should go to 0 automatically and it does not. The reason is, as Clive said, that some of the required clocks is not present. Note, that not only you need to configure them in RCC, you also need to physically present the clocks on respective pins (25MHz on MII_TX_CLK and MII_RX_CLK if MII is selected; 50MHz on RMII_REF_CK if RMII is selected).

JW

[Tesla DeLorean]

Posted on March 05, 2013 at 15:06

The Software was for the STM32F4x7 line.  But this example was listed by examples for STM32F407VG. I can't find any other example-projects for ethernet. It must be the right.

Assume for a moment that the software was not developed in a vacuum, and was tied to some specific hardware implementation, with some external PHY.

Does the board it was designed to work on use some specific PHY? Is that the same as the one you're using? Does that PHY generate a clock, or expect one? Are you configuring things correctly for your situation?

[widrat]

Posted on March 06, 2013 at 10:34

Ok I found the problem. The externel PHY was connected by the wrong PIN (it works but not with the standard program code by STM) with this reason clock is not present.

Thank you all for your help ;)

[Thomas_Socomec]

Posted on March 12, 2013 at 09:39

Hello,

I have a problem which may be similar to this one, maybe can you help me.

My mockup with STM32F207 used Ethernet (MAC) and SDcard (SDIO). All is working correctly, but if I start without the SDcard, the software loops in the wait for the DMABMR->SR register = 0.

Is it possible that the SDIO peripheral have a link with the MAC peripheral (maybe in the clock source) ?

Moreover, I see some strange behaviors with the CPU timestamp function, but I don't know if it can be linked.

Thank you ini advance.

Thomas

[Tesla DeLorean]

Posted on March 12, 2013 at 12:28

I think you need to look at your clock sources, and PLL settings.

Check if you are enabling the clocks on the right APB for each peripheral. You might want to look over the clock tree, and pin assignments for potential clashes.

If you provide hardware initialization code (clocks and pins) I can look that over.

[Thomas_Socomec]

Posted on March 12, 2013 at 17:20

Thank you for your answer.

The problem is solved : it was the power supply of the PHY which was not enabled...

Best regards

[balazs]

Posted on September 21, 2015 at 11:19

Hi,

I think I have a very similar problem.

Using an STM32F107 with a LAN8720A PHY with RMII integration the MAC reset sequence does not work, the code is stuck in the while loop checking for the reset bit:

/* Ethernet Software reset */

 

  /* Set the SWR bit: resets all MAC subsystem internal registers and logic */

 

  /* After reset all the registers holds their respective reset values */

 

  (heth->Instance)->DMABMR |= ETH_DMABMR_SR;

 

  

 

  /* Wait for software reset */

 

  while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)

 

  {

 

  }

The code has been generated specifically for this MCU using the STM32CubeMX IDE, following the clock configurations as per the reference manual:

25 MHz HSE  > Prediv2: /5 > VCOInput2: 5 > PLL2MUL x8 > Prediv1: /5 > PLL 8 x9 >PLLCLK: 72

 

 

PLL3MUL x10 > PLL3CLK: 50

 

 

MCO: PLL3CLK/1 = 50 MHz

 

PLL_VCO /3 = 48 MHz

Is there any other configurations I need to check? E.g. How is the MCU MAC getting the 50MHz internal clock signal if the system clock is running on 72 MHz?

Thank you,

Balas