STM32F4 Discovery 'Audio_playback_and_record' demo and reducing CPU clock.

[ruslan]

Posted on February 13, 2014 at 08:57

Dear Colleagues,

Thank you for the good Evaluation Kit. 

For one of the project I use 'Audio_playback_and_record' demo application as a reference. When I use default SYSCLK/HCLK 168 MHz the demo records audio, and I see pretty clear signal with no distortion.

Then I want to reduce CPU clock frequency to 84 MHz. So I use 'System Clock Configuration' Excel-tool to generate new system_stm32f4xx.c file. Then I copy/replace this file to '

Audio_playback_and_record

' project, recompile, download and run. I see that distortion occurs. If you need I can provide pictures by e-mail.

How can I record clear audio signal with CPU clock frequency lower than 168 MHz?

#stm32f4-audio-playback-custom

[chen]

Posted on February 13, 2014 at 10:38

Hi

''

How can I record clear audio signal with CPU clock frequency lower than 168 MHz?

''

You need to work out what the demo code is doing.

Is it using the ADC to digitise the sound?

What frequency (or sample rate) is the ADC sampling at?

Once you know the sample rate, you need to adjust the ADC clocking (see the clocking scheme diagram in the reference manual) to achieve the same sample rate.

Is the demo using the DAC to generate the output?

What frequency is the DAC using to output?

Adjust the DAC clocking to achieve the same frequence.

[ruslan]

Posted on February 14, 2014 at 00:48

Dear Sir,

Thank you for you quick response.

'Audio_playback_and_record' demo gathers data from MEMS I2S mic This mic provides me audio data in Pulse Density Modulation (PDM) format.

system_stm32f4xx.c file and Clock Configuration Tool are in charge of setting all clocks and frequencies automatically, and I do not need to adjust them manually by myself.

It seems STM32Discovery software cannot be a reference for low-power speech applications cause it works with maximum frequency 168 MHZ only.

I do not use output at my particular case at all.

Regards.

[Tesla DeLorean]

Posted on February 14, 2014 at 01:27

There's more than one clock, and options for the APB1/APB2 which would allow them to clock at 42 and 84 MHz respectively, regardless if the CPU clock is 168 MHz or 84 MHz.

[ruslan]

Posted on February 17, 2014 at 02:22

Thank you for your answers, but I fixed it other way.

I changed data buffering scheme and moved PDM filtering from ISR to main loop. So now demo can work at reduced frequencies.