STM32F334R8 ADC problem

[Santos]

Hello everyone!

I am trying to use the ADC of my NUCLEO-F334R8 board. I want to read the PC1 pin (ADC12, channel 7). I try to initialize the ADC with the following code:

void BSP_ADC_Init()
{
 // Enable GPIOC clock
 RCC->AHBENR |= RCC_AHBENR_GPIOCEN;

 // Configure pin PC1 as analog
 GPIOC->MODER &= ~GPIO_MODER_MODER1_Msk;
 GPIOC->MODER |= (0x03 << GPIO_MODER_MODER1_Pos);

 // Enable ADC clock
 RCC->AHBENR |= RCC_AHBENR_ADC12EN;

 // Reset ADC configuration
 ADC1->CR = 0x00000000;
 ADC1->CFGR = 0x00000000;
 ADC1->SQR1 = 0x00000000;

 // Enable continuous conversion mode
 ADC1->CFGR |= ADC_CFGR_CONT;

 // Select channel 7
 ADC1->SQR1 |= (0x07 << ADC_SQR1_SQ1_Pos);

 // Set sampling time to 19.5 ADC clock cycles
 ADC1->SMPR1 = (0x04 << ADC_SMPR1_SMP7_Pos);

 // 12-bit resolution
 ADC1->CFGR |= (0x00 << ADC_CFGR_RES_Pos);

 // Select PCLK/2 as ADC clock
 RCC->CFGR2 |= (0x11 << RCC_CFGR2_ADCPRE12_Pos);

 // Enable ADC
 ADC1->CR |= ADC_CR_ADEN;

 // Start conversion
 ADC1->CR |= ADC_CR_ADSTART;
}

But it seems not to work. In the main, I get stuck in the loop:

// Wait here until ADC EOC
while ((ADC1->ISR & ADC_ISR_EOC) != ADC_ISR_EOC);

EOC never sets and DR is always 0.

Could anyone help me?

 

[Saket_Om]

Hello @Santos 

Please follow the configuration provided in the LL example "Projects/STM32F334R8-Nucleo/Examples_LL/ADC/ADC_ContinuousConversion_TriggerSW".

 

 

[waclawek.jan]

By default, ADC clock is selected as asynchronous in ADCx_CCR.CKMODE. However, for asynchronous clock, you would need to set up PLL in RCC, and also set RCC_CFGR2.ADC12PRES to non-zero. Alternatively, set synchronous clock in ADCx_CCR.CKMODE.

JW

[Santos]

Thank you for your suggestion. I have already configured the PLL, and as you can see in my code, I have set RCC_CFGR2.ADC12PRES to a non-zero value (RCC->CFGR2 |= (0x11 << RCC_CFGR2_ADCPRE12_Pos)). Unfortunately, setting the synchronous clock in ADCx_CCR.CKMODE hasn't worked either.

[waclawek.jan]

Read out and check/post the ADC and RCC registers content.

JW

[Santos]

RCC_AHBENR: 0x100a0014

RCC_CFGR2: 0x110

ADC1_CR: 0x5

ADC1_CFGR: 0x2000

ADC1_SQR1: 0x1c0

ADC1_SMPR1: 0x800000

[waclawek.jan]

You don't have enabled ADVREGEN in ADC1_CR.

JW

[Santos]

I have just enabled it (ADC1_CR=0x10000005), but ADC still doesn't work.

[waclawek.jan]

Did you follow the procedures to set those bits, outlined in ADVREG enable sequence and Software procedure to enable the ADC subchapters of the ADC chapter in RM? In other words, you need to wait both after enabling ADCREG and ADEN (the former is just a software delay, the latter indicated by ADRDY).

JW

[Santos]

Yes, you are absolutely right. Specifically, I was missing the step of waiting for the ADRDY after enabling the ADC, before setting the ADSTART bit. Now everything is working fine. Thank you very much for your help.