stm32f070f6p6 Watchdog Reset Issue
I'm working with an STM32F070 and trying to verify the Independent Watchdog (IWDG). My expectation is that if the watchdog is not refreshed, the MCU should perform a system reset after the timeout expires.
The IWDG is configured as follows:
- MCU: STM32F070
- Clock:
- HSI = ON (System Clock)
- LSI = ON (for IWDG)
- IWDG configuration:
- Prescaler = 256
- Reload = 4095
- Window = 4095
- The watchdog is initialized using
HAL_IWDG_Init().
To force a timeout, I intentionally do not refresh the watchdog:
// IWDG_KICK();
while (1)
{
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_0, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_1, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_2, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_3, GPIO_PIN_RESET);
}The full initialization is:
hiwdg.Instance = IWDG;
hiwdg.Init.Prescaler = IWDG_PRESCALER_256;
hiwdg.Init.Reload = 4095;
hiwdg.Init.Window = 4095;
HAL_IWDG_Init(&hiwdg);According to the reference manual, with Prescaler = 256 and Reload = 4095, I expect a watchdog timeout of roughly 32 seconds (assuming LSI ≈ 32 kHz).
Observed behavior:
Instead of performing a watchdog reset, the MCU appears to hang. The LEDs stop responding, but the device never restarts. After the expected timeout, execution does not begin again from main(), and the reset flags do not indicate an obvious watchdog reset.
Questions:
- Is there any known STM32F070 or IWDG configuration issue that can prevent the watchdog from generating a reset?
- Are there option bytes, debug settings, or hardware conditions that can suppress an IWDG reset while allowing the watchdog counter to expire?
- Has anyone observed an STM32F070 entering a stalled state instead of resetting due to an IWDG timeout?
- What is the recommended method to verify that the IWDG reset signal is actually being generated (e.g., checking
RCC->CSR, NRST pin behavior with an oscilloscope, or other diagnostics)?
For completeness, my SystemClock_Config() enables both HSI and LSI, and HAL_IWDG_Init() returns HAL_OK without errors.
I'm looking for any suggestions on what to check next or whether there are hardware/debug configurations that could explain this behavior.
