SPI DMA request does not seem to take SPI BUSY flag into account, leading to corrupt data?

[haphi]

I implement a SPI slave protocol on a STM32F0 board.

After the master as transferred a command to the slave, it polls in regular intervals by reading one byte off the slave until the slave sends a start byte of value 0xFF.

in the attached screenshot, the bottom channel is pulled low immediately before the call to HAL_SPI_Transmit_DMA (flag A1). Shortly thereafter (20us) the master pulls the CSS line low and transfers one byte. However, it appears the shift register is overwritten during the transfer, leading to corrupt data (value 0x7F instead of 0xFF) transmitted.

It would appear that the DMA transfer to the SPI peripheral does not take the BUSY flag into account.

Is there a fix a or a workaroung for this issue that ensures data integrity? Since the slave has no control over when the master initiates a transfer, how can I ensure this kind of error does not occur?

[waclawek.jan]

https://st-microelectronics.jiveon.com/message/145754-spi-stm32f4xx-in-slave-mode-may-corrupt-first-tx-bit (not migrated... yet?)

[EDIT May 2020] https://community.st.com/s/feed/0D50X00009XkW6HSAV [/EDIT]

I was able to work it around only by keeping the slave SPI Tx buffer full all the time (feeding it with d�?mmy bytes between "real" transactions, and designing the protocol accordingly).

JW

[haphi]

Thank you, this appears to be the same error!

This is unfortunate, but I will manage with a simliar workaround.