PSSI with DMA on the STM32H7A

[Neuraleanus]

After an aborted attempt to get the PSSI interface on the STM32N6 to work with DMA, I have decided to try a different part, the STM32H7A.  Running into a similar problem attempting to get the DMA to work.

Here is a snap-shot of what I see:

After receiving HAL_OK from HAL_PSSI_Receive_DMA(). I get the error interrupt with an error code of 0.  As may be seen, there is a DMA Transfer error.  This is running on the Nucleo-H7A3ZI-Q board.  The clock tree has been changed to increase the clock speed:

The PSSI clock is produced by a PWM Timer and set to a frequency of 10MHz.  Data is from a 12 bit ADC with an active high Ready.  DE is not used.  I have a pull-up on Ready.  With HAL_PSSI_Receive_DMA() in a loop from a frame timer, each call returns HAL_OK followed by the error interrupt.

The PSSI setup:

The DMA setup:

I’ve been studying the examples given on this board for both the H5 and the H7.  Whereas the N6 produced an immediate error response to multiple PSSI DMA attempts, the H7A does not.  The DMA controller fails on both.  What is preventing the DMA from working?
 

 

[Neuraleanus]

Thinking that perhaps this is a memory access issue, I added the following;

To sram.icf :

define region D2_SRAM_region = mem:[from 0x30000000 to 0x3003FFFF];
place in D2_SRAM_region { section .dop_buffer};

To main.h:

#define DOP_BUFFER __attribute__((section(".dop_buffer")))

To main.c

// Input buffer
DOP_BUFFER short dop[INPUT_BUFFER_SIZE];

Unfortunately, there was no change.  I still get the DMA Transfer error.

I need to allocate a 20K byte buffer.  The AHB SRAM seems like a good place for this.

Correction: 

I relocated define region D2_SRAM_region = mem:[from 0x30000000 to 0x3003FFFF];
place in D2_SRAM_region { section .dop_buffer};

to flash.icf and the Transfer error has gone away and DMA appears to work.

Correct to my previous correction:

I am now getting both the Transfer complete and Error interrupts.  Both the DMA and PSSI error codes are 0.

[Neuraleanus]

Yes, this issue appears to have been resolved.  STM Micro needs to do a better job documenting the memory architecture.  Namely, what peripherals may communicate to which memories.  To the programmer, it looks like the memory is organized as a single block, but it is actually anything but.