Question
PLL initialization defect on Nucleo F767ZI
In main.c, SystemClock_Config(), the PLL is set up as follows:
...
RCC_OscInitStruct.PLL.PLLM = 25;
RCC_OscInitStruct.PLL.PLLN = 400;
...
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
...
The implication is that the clock is 25MHz, and being divided down to 1MHz as input to the VCO. However, by default the input clock is actually 8MHz supplied by the ST-Link. The effect is to run the PLL CLK at 64MHz, instead of the implied 200MHz.
Note that this is definitely wrong, not just a subjective decision to run the clock slower, because the reference manual indicates that the VCO input frequency range should be between 1MHz and 2MHz.
