Question
Issue in USB_CoreReset() occasionally fails in debug mode H743
On the H743 using V1.12.1 library, CubeIDE, the USB_CoreReset() procedure occasionally fails to reset the Host USB core in debug mode. I have added a reset call which seems to fix the issue in debug, reproduced below.
I would like to know if this is a known issue in CubeIDE debug mode?
See fix below in USB_CoreReset()
// mod - added extra reset as in debug the USB host core fails to reset correctly at times
static void USB_Hard_Reset(USB_OTG_GlobalTypeDef *USBx)
{
/* Example from USBH_LL_Init() in usbh_conf.c USB_HOST/Target/
__HAL_RCC_USB_OTG_HS_FORCE_RESET();
HAL_Delay(50);
__HAL_RCC_USB_OTG_HS_RELEASE_RESET();
HAL_Delay(50);
/* --- FS BACK-POWER FIX START ---
HAL_PWREx_EnableUSBVoltageDetector();
uint32_t to = 100000;
while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY) == 0U && to--) ;
assert(to > 0);*/
uint32_t timeout;
/* 1. Mask all interrupts and stop AHB transactions */
USBx->GINTMSK = 0U;
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; // disable global int
/* 2. Wait for AHB idle */
timeout = 0xFFFFU;
while (((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U) && (timeout-- > 0U))
{
/* wait */
}
/* 3. Core soft reset */
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
timeout = 0xFFFFU;
while (((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) != 0U) && (timeout-- > 0U))
{
/* wait */
}
/* 4. Flush TX FIFOs */
USBx->GRSTCTL = USB_OTG_GRSTCTL_TXFFLSH | (0x10U << 6); // all TX FIFOs
timeout = 0xFFFFU;
while (((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) != 0U) && (timeout-- > 0U))
{
/* wait */
}
/* 5. Flush RX FIFO */
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
timeout = 0xFFFFU;
while (((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) != 0U) && (timeout-- > 0U))
{
/* wait */
}
/* 6. Clear pending core interrupts */
USBx->GINTSTS = 0xFFFFFFFFU;
/* 7. Leave core in clean, disabled state.
Higher-level init (host/device, FIFOs, GCCFG, etc.) must be redone after this. */
}
Affected stock HAL routine:-
/**
* @brief Reset the USB Core (needed after USB clock settings change)
* @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
{
#ifdef DEBUG // mod - added to overcome debug mode HOST HS core hang
USB_Hard_Reset(USBx);
#endif
__IO uint32_t count = 0U;
/* Wait for AHB master IDLE state. */
do
{
count++;
if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U);
/* Core Soft Reset */
count = 0U;
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
do
{
count++;
// BUG IN DEBUG MODE?? SOMETIMES TIMES-OUT IN DEBUG MODE THEM USB HOST FAILS TO WORK
if (count > HAL_USB_TIMEOUT)
{
return HAL_TIMEOUT;
}
} while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
return HAL_OK;
}
