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Lmatt.11
Associate III
December 14, 2021
Solved

If I want to use UCPD2 in STM32G0B1RCT6, is HSI16 the only choice as the driving clock for this integrated PD controller? May i use HSE?

  • December 14, 2021
  • 3 replies
  • 2598 views

In my application, UCPD2 will be active for USB type C PD Sink (45W), which will be working together with other peripherals, such as timers, USB(DEVICE), etc.

 0693W00000HoVNTQA3.pngIf the driving clock for UCPD2 is HSI16(in datasheet described), if no other choice, that means i have to use the HSI clock source for the whole projects. That means there are no chance to choose HSE. Is that correct?

But actually, PD is only a part of the system, not the whole in my application. Could you please gibe me some suggestions?

Thanks.

This topic has been closed for replies.
Best answer by Peter BENSCH

The following statement can be found in RM0444, section 38.4.2 for the clocks for UCPD:

The register section is clocked with the APB clock (ucpd_pclk).

The main functional part of the transmitter is clocked with ucpd_clk clock, pre-scaled from the ucpd_ker_ck (HSI16) clock according to the PSC_USBPDCLK[2:0] bitfield of the UCPD_CFGR1 register.

The main functional part of the receiver is clocked with the ucpd_rx_clk recovered from the incoming bitstream.

Does this answer your question?

Regards

/Peter

3 replies

Muhammed Güler
Senior III
December 14, 2021

From the Clock Config page in CubeMX, you can choose which hardware will use which frequency and source. Both SYSCLK and USBCLK should be fed with HSE + PLL. You don't have to use HSI.

Peter BENSCH
Peter BENSCHBest answer
ST Technical Moderator
December 14, 2021

The following statement can be found in RM0444, section 38.4.2 for the clocks for UCPD:

The register section is clocked with the APB clock (ucpd_pclk).

The main functional part of the transmitter is clocked with ucpd_clk clock, pre-scaled from the ucpd_ker_ck (HSI16) clock according to the PSC_USBPDCLK[2:0] bitfield of the UCPD_CFGR1 register.

The main functional part of the receiver is clocked with the ucpd_rx_clk recovered from the incoming bitstream.

Does this answer your question?

Regards

/Peter

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Lmatt.11
Lmatt.11Author
Associate III
December 14, 2021

@Peter,

Thanks a lot for your info..

I also saw this, that means the HSI must be enable, if not the PD controller will not work normally.

0693W00000HoVyPQAV.png I worried about the stability when the HSI running in high temperature, for example nearby the higher limit of range(-40°C to 85°C/105°C/125°C, the operating temperture for STM32g0b1rc). For the device may work in a high temperature circumstance.

But have no choice, hope it's superfluous:smiling_face_with_smiling_eyes:.

Thanks again.